From d762fe41635057a7a0bb14dcd1020b0adbcc75b6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 3 Aug 2020 18:02:13 +0100 Subject: [PATCH] move debug to record --- src/soc/debug/dmi.py | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/src/soc/debug/dmi.py b/src/soc/debug/dmi.py index 102afab2..2a72786f 100644 --- a/src/soc/debug/dmi.py +++ b/src/soc/debug/dmi.py @@ -59,6 +59,15 @@ class DMIInterface(RecordObject): self.ack_o = Signal() # DMI ack request +class DbgReg(RecordObject): + def __init__(self, name): + super().__init__(name=name) + self.req_o = Signal() + self.ack_i = Signal() + self.addr_o = Signal(7) # includes fast SPRs, others? + self.data_i = Signal(64) + + class CoreDebug(Elaboratable): def __init__(self, LOG_LENGTH=0): # TODO - debug log 512): # Length of log buffer @@ -77,10 +86,7 @@ class CoreDebug(Elaboratable): self.msr = Signal(64) # GSPR register read port - self.dbg_gpr_req_o = Signal() - self.dbg_gpr_ack_i = Signal() - self.dbg_gpr_addr_o = Signal(7) # includes fast SPRs, others? - self.dbg_gpr_data_i = Signal(64) + self.dbg_gpr = DbgReg("dbg_gpr") # Core logging data self.log_data_i = Signal(256) @@ -109,7 +115,7 @@ class CoreDebug(Elaboratable): do_icreset = Signal() terminated = Signal() do_gspr_rd = Signal() - gspr_index = Signal.like(self.dbg_gpr_addr_o) + gspr_index = Signal.like(self.dbg_gpr.addr_o) log_dmi_addr = Signal(32) log_dmi_data = Signal(64) @@ -121,8 +127,8 @@ class CoreDebug(Elaboratable): # Single cycle register accesses on DMI except for GSPR data comb += self.dmi.ack_o.eq(Mux(self.dmi.addr_i == DBGCore.GSPR_DATA, - self.dbg_gpr_ack_i, self.dmi.req_i)) - comb += self.dbg_gpr_req_o.eq(Mux(self.dmi.addr_i == DBGCore.GSPR_DATA, + self.dbg_gpr.ack_i, self.dmi.req_i)) + comb += self.dbg_gpr.req_o.eq(Mux(self.dmi.addr_i == DBGCore.GSPR_DATA, self.dmi.req_i, 0)) # Status register read composition (DBUG_CORE_STAT_xxx) @@ -139,7 +145,7 @@ class CoreDebug(Elaboratable): with m.Case( DBGCore.MSR): comb += self.dmi.dout.eq(self.msr) with m.Case( DBGCore.GSPR_DATA): - comb += self.dmi.dout.eq(self.dbg_gpr_data_i) + comb += self.dmi.dout.eq(self.dbg_gpr.data_i) with m.Case( DBGCore.LOG_ADDR): comb += self.dmi.dout.eq(Cat(log_dmi_addr, self.log_write_addr_o)) @@ -206,7 +212,7 @@ class CoreDebug(Elaboratable): sync += stopping.eq(1) sync += terminated.eq(1) - comb += self.dbg_gpr_addr_o.eq(gspr_index) + comb += self.dbg_gpr.addr_o.eq(gspr_index) # Core control signals generated by the debug module comb += self.core_stop_o.eq(stopping & ~do_step) @@ -309,10 +315,7 @@ class CoreDebug(Elaboratable): yield self.core_stopped_i yield self.nia yield self.msr - yield self.dbg_gpr_req_o - yield self.dbg_gpr_ack_i - yield self.dbg_gpr_addr_o - yield self.dbg_gpr_data_i + yield from self.dbg_gpr yield self.log_data_i yield self.log_read_addr_i yield self.log_read_data_o -- 2.30.2