From d769d537d32fe695168a6e0ea9f4d9ad34cf61d1 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 25 May 2023 14:28:25 +0100
Subject: [PATCH] add hypothetical sv.addi page explaining why DWIs must not be
 different see https://bugs.libre-soc.org/show_bug.cgi?id=1056#c12

---
 openpower/sv/ls010/hypothetical_addi.mdwn | 73 +++++++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 openpower/sv/ls010/hypothetical_addi.mdwn

diff --git a/openpower/sv/ls010/hypothetical_addi.mdwn b/openpower/sv/ls010/hypothetical_addi.mdwn
new file mode 100644
index 000000000..f2f59320b
--- /dev/null
+++ b/openpower/sv/ls010/hypothetical_addi.mdwn
@@ -0,0 +1,73 @@
+# Example demonstration instruction modified to SVP64 (badly)
+
+Although split-fields are used in PO1-Prefixing, and it is reasonable
+to expect to clarify "in-situ" the behaviour of `{MLS:D-form}`
+instructions as opposed to `{D-Form}` instructions, there are reasons
+why doing the same for PO9-Prefixed SV instructions is neither safe
+nor sensible.  These are illustrated through a hypothetically-proposed
+extension to `addi` / `paddi` (Public v3.1 I 3.3.9 p76).
+
+* Firstly in SV, it is prohibited from adding new operands.
+  `addi RT,RA,SI` may **only** be extended to `sv.addi RT,RA,SI`.
+* Secondly, the field positions and bits are also prohibited from
+  being changed merely because of a PO9-Prefix.
+
+**Add Immediate** D-Form
+
+* addi RT,RA,SI
+
+```
+    DWI:
+        |    14 |   RT            |    RA       |     SI       |
+        | 0     | 6               | 11          | 16        31 |
+```
+
+**Prefixed Add Immediate** MLS:D-form
+
+* paddi RT,RA,SI,R
+
+```
+    Prefix:
+        |    1  |   2    | 0 | // | R  | //  |     si0         |
+        | 0     | 6      | 8 | 9  | 11 | 12  | 14           31 |
+
+    Suffix::
+        |    14 |   RT            |    RA       | si1          |
+        | 0     | 6               | 11          | 16        31 |
+```
+
+**Vectorized Add Immediate** SVRM-Normal:D-form
+
+* sv.addi RT,RA,SI
+
+```
+    Prefix:
+        |    9  |  ..    |     Stuff | EXTRA    | MODEBITS     |
+        | 0     | 6      | 8         | 17    26 | 27        31 |
+    Suffix:
+        |    14 |   RT            |    RA       |     SI       |
+        | 0     | 6               | 11          | 16        31 |
+```
+
+Pseudo-code:
+
+```
+    if "addi" then
+        RT <- (RA|0) + EXTS64(SI)
+    if "paddi" & R=0 then
+        RT <- (RA|0) + EXTS64(si0||si1)
+    if "paddi" & R=1 then
+        RT <- CIA + EXTS64(si0||si1)
+    if "sv.addi" then # beginning of spec writer nightmare
+        # spec writer's worst nightmare unfolds here
+        svra <- DECODE_WITH_EXTRA3(Suffix.D-Form.RA, EXTRA[0:2])
+        svrt <- DECODE_WITH_EXTRA3(Suffix.D-Form.RT, EXTRA[3:5])
+        svsi <- Suffix.D-Form.SI
+        # finally got to the actual add which is exactly the same as "addi"
+        GPR(svrt) <- (svra|0) + EXTS64(svsi)
+```
+
+Special Registers Altered:
+
+    None
+
-- 
2.30.2