From d7768aabbd433c649301acf31829b54b0617c906 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 18 Jul 2020 10:07:25 +0100 Subject: [PATCH] corrections to trap main_stage.py OP_RFID according to reading spec --- src/soc/fu/trap/main_stage.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index 325fb373..e5ea4cd2 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -201,9 +201,9 @@ class TrapMainStage(PipeModBase): msr_check_pr(m, msr_o.data) # hypervisor stuff - comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV] & srr1_i[MSR.HV]) - comb += msr_o.data[MSR.ME].eq((msr_i[MSR.HV] & srr1_i[MSR.HV]) | - (~msr_i[MSR.HV] & srr1_i[MSR.HV])) + with m.If(msr_i[MSR.HV]): + comb += msr_o.data[MSR.HV].eq(srr1_i[MSR.HV]) + comb += msr_o.data[MSR.ME].eq(srr1_i[MSR.ME]) # don't understand but it's in the spec with m.If((msr_i[63-31:63-29] != Const(0b010, 3)) | (srr1_i[63-31:63-29] != Const(0b000, 3))): -- 2.30.2