From d77ea9f299398cbd12eda5b012dcecadb1927704 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 28 May 2020 11:33:20 +0100 Subject: [PATCH] update comment --- src/soc/fu/common_output_stage.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py index 147c891e..efeb42a9 100644 --- a/src/soc/fu/common_output_stage.py +++ b/src/soc/fu/common_output_stage.py @@ -43,7 +43,7 @@ class CommonOutputStage(PipeModBase): cr0 = Signal(4, reset_less=True) # TODO: if o[63] is XORed with "operand == OP_CMP" - # that can be used as a test + # that can be used as a test of whether to invert the +ve/-ve test # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60 comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP) -- 2.30.2