From d78024793ceb20c8df0dbeb3e642f1764d7963a6 Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Fri, 19 Nov 2021 20:10:18 +0000 Subject: [PATCH] Added code from jtag srv test, not working --- src/spec/testing_stage1.py | 51 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py index f7dc99c..c9151aa 100644 --- a/src/spec/testing_stage1.py +++ b/src/spec/testing_stage1.py @@ -7,6 +7,18 @@ from collections import OrderedDict from jtag import JTAG, resiotypes from copy import deepcopy +# extra dependencies for jtag testing (?) +from soc.bus.sram import SRAM + +from nmigen import Memory +from nmigen.pysim import Simulator, Delay, Settle, Tick + +from nmutil.util import wrap + +from soc.debug.jtagutils import (jtag_read_write_reg, + jtag_srv, jtag_set_reset, + jtag_set_ir, jtag_set_get_dr) + # Was thinking of using these functions, but skipped for simplicity for now # XXX nope. the output from JSON file. #from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi, @@ -398,3 +410,42 @@ resources = create_resources(pinset) p = ASICPlatform (resources, top.jtag) p.build(top) +# dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync") +top.jtag.stop = False +# rather than the client access the JTAG bus directly +# create an alternative that the client sets +class Dummy: pass +cdut = Dummy() +cdut.cbus = JTAGInterface() + +# set up client-server on port 44843-something +top.jtag.s = JTAGServer() +if len(sys.argv) != 2 or sys.argv[1] != 'server': + cdut.c = JTAGClient() + top.jtag.s.get_connection() +else: + print ("running server only as requested, use openocd remote to test") + sys.stdout.flush() + top.jtag.s.get_connection(None) # block waiting for connection + +# take copy of ir_width and scan_len +cdut._ir_width = top.jtag._ir_width +cdut.scan_len = top.jtag.scan_len + +memory = Memory(width=64, depth=16) +sram = SRAM(memory=memory, bus=dut.wb) + +#m = Module() +#m.submodules.ast = dut +#m.submodules.sram = sram + +sim = Simulator(top) +sim.add_clock(1e-6, domain="sync") # standard clock + +sim.add_sync_process(wrap(jtag_srv(top))) #? jtag server +if len(sys.argv) != 2 or sys.argv[1] != 'server': + sim.add_sync_process(wrap(jtag_sim(cdut, top.jtag))) # actual jtag tester +sim.add_sync_process(wrap(dmi_sim(top.jtag))) # handles (pretends to be) DMI + +with sim.write_vcd("dmi2jtag_test_srv.vcd"): + sim.run() -- 2.30.2