From d7967c3c21fbf1d37f200b9284232aec15a7fadd Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Fri, 11 Nov 2022 00:52:36 -0800 Subject: [PATCH] add maddedus --- openpower/isa/svfixedarith.mdwn | 26 ++++++++++++++ openpower/isatables/RM-1P-3S1D.csv | 1 + openpower/isatables/minor_4.csv | 1 + src/openpower/decoder/isa/caller.py | 2 +- src/openpower/decoder/power_decoder2.py | 1 + src/openpower/decoder/power_enums.py | 2 +- src/openpower/sv/trans/svp64.py | 1 + src/openpower/test/bigint/bigint_cases.py | 44 +++++++++++++++++++++++ 8 files changed, 76 insertions(+), 2 deletions(-) diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn index c7050133..1b6efd49 100644 --- a/openpower/isa/svfixedarith.mdwn +++ b/openpower/isa/svfixedarith.mdwn @@ -18,6 +18,32 @@ Special Registers Altered: None +# [DRAFT] Multiply and Add Extended Doubleword Unsigned Signed + +VA-Form + +* maddedus RT,RA,RB,RC + +Pseudo-code: + + + prod[0:XLEN*2-1] <- [0] * (XLEN * 2) + if (RB)[0] != 0 then + prod[0:XLEN*2-1] <- -((RA) * -(RB)) + else + prod[0:XLEN*2-1] <- (RA) * (RB) + + sum[0:XLEN*2-1] <- prod + (EXTSXL((RC)[0], 1) || (RC)) + RT <- sum[XLEN:2*XLEN-1] + RS <- sum[0:XLEN-1] + +Special Registers Altered: + + None + # [DRAFT] Divide/Modulo Double-width Doubleword Unsigned VA-Form diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv index 09eebc6a..9a3c6c15 100644 --- a/openpower/isatables/RM-1P-3S1D.csv +++ b/openpower/isatables/RM-1P-3S1D.csv @@ -35,6 +35,7 @@ maddhd,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 maddhdu,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 maddedu,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 maddld,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 +maddedus,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 divmod2du,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0 absdacs,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 absdacu,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 diff --git a/openpower/isatables/minor_4.csv b/openpower/isatables/minor_4.csv index b2426340..3121bd7c 100644 --- a/openpower/isatables/minor_4.csv +++ b/openpower/isatables/minor_4.csv @@ -4,6 +4,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 48,ALU,OP_MADDHD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhd,VA,,, 49,ALU,OP_MADDHDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhdu,VA,,, 50,ALU,OP_MADDEDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddedu,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg +57,ALU,OP_MADDEDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddedus,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg 51,ALU,OP_MADDLD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddld,VA,,, 58,ALU,OP_DIVMOD2DU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,divmod2du,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg 56,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index fd2cdc3f..885510f4 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1777,7 +1777,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): 'grev', 'ternlogi', 'bmask', 'cprop', 'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd', 'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du", - "dsld", "dsrd", + "dsld", "dsrd", "maddedus", "shadd", "shadduw", ]: illegal = False diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index ad42f80e..1b00e24d 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1059,6 +1059,7 @@ class PowerDecodeSubset(Elaboratable): with m.If((major == 4) & xo6.matches( '111000', # pcdec '110010', # maddedu + '111001', # maddedus '111010', # divmod2du '11010-', # dsld '11011-', # dsrd diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 0ffa7550..699c5d89 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -549,7 +549,7 @@ _insns = [ "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word # "lwabr", # load word SVP64 bit-reversed # "lwzbr", "lwzubr", # more load word SVP64 bit-reversed - "maddedu", + "maddedu", "maddedus", "maddhd", "maddhdu", "maddld", # INT multiply-and-add "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs "mfmsr", "mfspr", diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index fb9dc6e2..c61e9283 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -566,6 +566,7 @@ def fishmv(fields): @_custom_insns( _insn("maddedu", XO=50), + _insn("maddedus", XO=57), _insn("divmod2du", XO=58), _insn("pcdec.", XO=56), ) diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py index 24050fbb..3c83fd57 100644 --- a/src/openpower/test/bigint/bigint_cases.py +++ b/src/openpower/test/bigint/bigint_cases.py @@ -3,6 +3,7 @@ from openpower.sv.trans.svp64 import SVP64Asm from openpower.test.state import ExpectedState from openpower.simulator.program import Program from openpower.decoder.isa.caller import SVP64State +from openpower.decoder.helpers import exts _SHIFT_TEST_RANGE = list(range(-64, 128, 16)) + [1, 63] _MASK32 = ((2 ** 32) - 1) @@ -37,6 +38,18 @@ class BigIntCases(TestAccumulatorBase): e.intregs[7] = (gprs[5] * gprs[6] + gprs[7]) >> 64 self.add_case(Program(lst, False), gprs, expected=e) + def case_maddedus(self): + lst = list(SVP64Asm(["maddedus 3,5,6,7"])) + gprs = [0] * 32 + gprs[5] = 0x8123456789ABCDEF + gprs[6] = 0xFEDCBA9876543210 + gprs[7] = 0x82468ACE13579BDF + e = ExpectedState(pc=4, int_regs=gprs) + v = gprs[5] * exts(gprs[6], 64) + exts(gprs[7], 64) + e.intregs[3] = v % 2 ** 64 + e.intregs[7] = (v >> 64) % 2 ** 64 + self.add_case(Program(lst, False), gprs, expected=e) + def case_divmod2du(self): lst = list(SVP64Asm(["divmod2du 3,5,6,7"])) gprs = [0] * 32 @@ -291,6 +304,37 @@ class SVP64BigIntCases(TestAccumulatorBase): e.intregs[4] = 0x1357 # 64-bit carry-out self.add_case(prog, gprs, expected=e, initial_svstate=svstate) + def case_sv_unsigned_bigint_mul_by_signed_scalar(self): + """performs a carry-rollover-vector-mul-with-add with a scalar, + using "RC" as a 64-bit carry in/out. + outputs are negative of sv.maddedu test. + + r18 r17 r16 + 0x1234_0000_5678_0000 0x9ABC_0000_DEF0_0000 0x1357_0000_9BDF_0000 * + r3 (scalar factor) -0x1_0001 + + r4 (carry in) -0xFEDC = + -0x1234_1234_5678_5678_9ABC_9ABC_DEF0_DEF0_1357_1357_9BDF_9BDF_FEDC = + r18 r17 r16 + 0xEDCB_A987_A987_6543 0x6543_210F_210F_ECA8 0xECA8_6420_6420_0124 + r4 (carry out) 0xFFFF_FFFF_FFFF_EDCB + """ + prog = Program(list(SVP64Asm(["sv.maddedus *16,*16,3,4"])), False) + gprs = [0] * 32 + gprs[16] = 0x1357_0000_9BDF_0000 # vector... + gprs[17] = 0x9ABC_0000_DEF0_0000 # ... + gprs[18] = 0x1234_0000_5678_0000 # ... input + gprs[3] = -0x1_0001 % 2 ** 64 # scalar multiplier + gprs[4] = -0xFEDC % 2 ** 64 # 64-bit carry-in + svstate = SVP64State() + svstate.vl = 3 + svstate.maxvl = 3 + e = ExpectedState(pc=8, int_regs=gprs) + e.intregs[16] = 0xECA8_6420_6420_0124 # vector... + e.intregs[17] = 0x6543_210F_210F_ECA8 # ... + e.intregs[18] = 0xEDCB_A987_A987_6543 # ... result + e.intregs[4] = 0xFFFF_FFFF_FFFF_EDCB # 64-bit carry-out + self.add_case(prog, gprs, expected=e, initial_svstate=svstate) + def case_sv_bigint_div_by_scalar(self): """performs a carry-rollover-vector-divmod with a scalar, using "RC" as a 64-bit carry. matched with the sv.maddedu -- 2.30.2