From d7c6c2f343b350e324e9db57fa9e04671f45bd18 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 11 Sep 2020 14:36:13 +0100 Subject: [PATCH] simplify dcache pending --- src/soc/experiment/dcache.py | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 78ebf744..b5df6b78 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -441,7 +441,7 @@ class DTLBUpdate(Elaboratable): class DCachePendingHit(Elaboratable): def __init__(self, tlb_pte_way, tlb_valid_way, tlb_hit_way, - cache_valid_bits, cache_tag_set, + cache_valid_idx, cache_tag_set, req_addr, hit_set): @@ -457,7 +457,7 @@ class DCachePendingHit(Elaboratable): self.tlb_hit_way = tlb_hit_way self.tlb_pte_way = tlb_pte_way self.tlb_valid_way = tlb_valid_way - self.cache_valid_bits = cache_valid_bits + self.cache_valid_idx = cache_valid_idx self.cache_tag_set = cache_tag_set self.req_addr = req_addr self.hit_set = hit_set @@ -472,7 +472,7 @@ class DCachePendingHit(Elaboratable): is_hit = self.is_hit tlb_pte_way = self.tlb_pte_way tlb_valid_way = self.tlb_valid_way - cache_valid_bits = self.cache_valid_bits + cache_valid_idx = self.cache_valid_idx cache_tag_set = self.cache_tag_set req_addr = self.req_addr tlb_hit_way = self.tlb_hit_way @@ -505,7 +505,7 @@ class DCachePendingHit(Elaboratable): for i in range(NUM_WAYS): is_tag_hit = Signal() - comb += is_tag_hit.eq(go & cache_valid_bits[req_index][i] & + comb += is_tag_hit.eq(go & cache_valid_idx[i] & (read_tag(i, cache_tag_set) == s_tag) & tlb_valid_way[j]) with m.If(is_tag_hit): @@ -523,7 +523,7 @@ class DCachePendingHit(Elaboratable): comb += s_tag.eq(get_tag(req_addr)) for i in range(NUM_WAYS): is_tag_hit = Signal() - comb += is_tag_hit.eq(go & cache_valid_bits[req_index][i] & + comb += is_tag_hit.eq(go & cache_valid_idx[i] & read_tag(i, cache_tag_set) == s_tag) with m.If(is_tag_hit): comb += hit_way.eq(i) @@ -792,6 +792,7 @@ class DCache(Elaboratable): go = Signal() nc = Signal() hit_set = Array(Signal() for i in range(TLB_NUM_WAYS)) + cache_valid_idx = Signal(INDEX_BITS) # Extract line, row and tag from request comb += req_index.eq(get_index(r0.req.addr)) @@ -799,10 +800,11 @@ class DCache(Elaboratable): comb += req_tag.eq(get_tag(ra)) comb += go.eq(r0_valid & ~(r0.tlbie | r0.tlbld) & ~r1.ls_error) + comb += cache_valid_idx.eq(cache_valid_bits[req_index]) m.submodules.dcache_pend = dc = DCachePendingHit(tlb_pte_way, tlb_valid_way, tlb_hit_way, - cache_valid_bits, cache_tag_set, + cache_valid_idx, cache_tag_set, r0.req.addr, hit_set) -- 2.30.2