From d7c71335c2a5bd65ee36b927af83ef97a1e06620 Mon Sep 17 00:00:00 2001 From: Alan Modra Date: Mon, 26 Oct 2020 21:51:31 +1030 Subject: [PATCH] [RS6000] Replace -mcpu with -mdejagnu-cpu * gcc.target/powerpc/pr93122.c: Replace -mcpu with -mdejagnu-cpu. * gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise. * gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise. * gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise. * gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise. --- gcc/testsuite/gcc.target/powerpc/pr93122.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/gcc/testsuite/gcc.target/powerpc/pr93122.c b/gcc/testsuite/gcc.target/powerpc/pr93122.c index 8ea4eb6a48b..97bcb0cea5f 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr93122.c +++ b/gcc/testsuite/gcc.target/powerpc/pr93122.c @@ -1,7 +1,7 @@ /* PR target/93122 */ /* { dg-require-effective-target power10_ok } */ /* { dg-do compile { target lp64 } } */ -/* { dg-options "-fstack-clash-protection -mprefixed -mcpu=power10" } */ +/* { dg-options "-fstack-clash-protection -mprefixed -mdejagnu-cpu=power10" } */ void bar (char *); diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c index 6ac4ed2173f..6aa165c675c 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c @@ -1,6 +1,6 @@ /* { dg-do run { target { power10_hw } } } */ /* { dg-do link { target { ! power10_hw } } } */ -/* { dg-options "-mcpu=power10 -O2" } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ /* { dg-require-effective-target { int128 && power10_ok } } */ /* Check that the expected 128-bit instructions are generated if the processor diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c index 05fedf77eb9..9fdfa4a8b82 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c @@ -1,6 +1,6 @@ /* { dg-do run { target { power10_hw } } } */ /* { dg-do link { target { ! power10_hw } } } */ -/* { dg-options "-mcpu=power10 -O2" } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ /* { dg-require-effective-target { int128 && power10_ok } } */ /* Check that the expected 128-bit instructions are generated if the processor diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c index 6e952695905..a038e56c9cd 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c @@ -1,6 +1,6 @@ /* { dg-do run { target { power10_hw } } } */ /* { dg-do link { target { ! power10_hw } } } */ -/* { dg-options "-mcpu=power10 -O2" } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ /* { dg-require-effective-target { int128 && power10_ok } } */ /* Check that the expected 128-bit instructions are generated if the processor diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c index c2eb53d3bb2..6f87e60ea41 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c @@ -1,6 +1,6 @@ /* { dg-do run { target { power10_hw } } } */ /* { dg-do link { target { ! power10_hw } } } */ -/* { dg-options "-mcpu=power10 -O2" } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ /* { dg-require-effective-target { int128 && power10_ok } } */ /* Check that the expected 128-bit instructions are generated if the processor -- 2.30.2