From d7c7474670b533df18dbdf1c080c98da2d6fad00 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 4 Apr 2018 15:40:53 +0200 Subject: [PATCH] gen/sim: fix import to use litex simulator instead of migen simulator --- litex/gen/sim/__init__.py | 2 +- litex/gen/sim/core.py | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/litex/gen/sim/__init__.py b/litex/gen/sim/__init__.py index e04060e1..853486a6 100644 --- a/litex/gen/sim/__init__.py +++ b/litex/gen/sim/__init__.py @@ -1 +1 @@ -from migen.sim.core import Simulator, run_simulation, passive +from litex.gen.sim.core import Simulator, run_simulation, passive diff --git a/litex/gen/sim/core.py b/litex/gen/sim/core.py index e3db45f6..2ba0cebc 100644 --- a/litex/gen/sim/core.py +++ b/litex/gen/sim/core.py @@ -14,7 +14,8 @@ from migen.fhdl.simplify import MemoryToArray from migen.fhdl.specials import _MemoryLocation from migen.fhdl.module import Module from migen.genlib.resetsync import AsyncResetSynchronizer -from migen.sim.vcd import VCDWriter, DummyVCDWriter + +from litex.gen.sim.vcd import VCDWriter, DummyVCDWriter class ClockState: -- 2.30.2