From d8132b5efa033068df6c805ee295415ecbcc68fe Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 21 May 2020 20:56:08 +0100 Subject: [PATCH] whitespace cleanup --- src/soc/fu/cr/main_stage.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py index 98d10cfa..7240ebe5 100644 --- a/src/soc/fu/cr/main_stage.py +++ b/src/soc/fu/cr/main_stage.py @@ -86,7 +86,7 @@ class CRMainStage(PipeModBase): ba = Signal(2, reset_less=True) bb = Signal(2, reset_less=True) - # Stupid bit ordering stuff + # Stupid bit ordering stuff. Because POWER. comb += bt.eq(3-BT[0:2]) comb += ba.eq(3-BA[0:2]) comb += bb.eq(3-BB[0:2]) -- 2.30.2