From d8275e99ffc00f971af782d2a7236b28ecbd9843 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 16 Jul 2018 12:14:19 +0100 Subject: [PATCH] pep8 whitespace cleanup --- src/bsv/interface_decl.py | 2 +- src/bsv/pinmux_generator.py | 25 ++++++++++++------------- src/myhdlgen/pinmux_generator.py | 2 +- src/myhdlgen/pins.py | 10 +++++----- src/parse.py | 4 ++-- 5 files changed, 21 insertions(+), 22 deletions(-) diff --git a/src/bsv/interface_decl.py b/src/bsv/interface_decl.py index a4e3e75..52e1ade 100644 --- a/src/bsv/interface_decl.py +++ b/src/bsv/interface_decl.py @@ -124,7 +124,7 @@ class Interface(object): for p in pinspecs: _p = {} _p.update(p) - if _p.has_key('type'): + if 'type' in _p: del _p['type'] if p.get('outen') is True: # special case, generate 3 pins del _p['outen'] diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py index 9fe54eb..ae081f7 100644 --- a/src/bsv/pinmux_generator.py +++ b/src/bsv/pinmux_generator.py @@ -305,34 +305,33 @@ def write_bvp(bvp, p, ifaces): # ######## Generate bus transactors ################ gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config\n;' \ '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;' - muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \ - '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;' + muxcfg = '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \ + '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;' gpiodec = '\tGPIO#({0} mygpio{1} <- mkgpio();' - muxdec = '\tMUX#({0} mymux{1} <- mkgpio();' + muxdec = '\tMUX#({0} mymux{1} <- mkgpio();' gpioifc = '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \ '\tinterface bank{0}A_slave=mygpio{0}.axi_slave;' - muxifc = '\tinterface muxb{0}_config=mymux{0}.pad_config;\n' \ - '\tinterface muxb{0}A_slave=mymux{0}.axi_slave;' + muxifc = '\tinterface muxb{0}_config=mymux{0}.pad_config;\n' \ + '\tinterface muxb{0}A_slave=mymux{0}.axi_slave;' with open(bvp, 'w') as bsv_file: # assume here that all muxes have a 1:1 gpio cfg = [] decl = [] idec = [] - iks = ifaces.keys() - iks.sort() + iks = sorted(ifaces.keys()) for iname in iks: - if not iname.startswith('gpio'): # TODO: declare other interfaces + if not iname.startswith('gpio'): # TODO: declare other interfaces continue bank = iname[4:] ifc = ifaces[iname] npins = len(ifc.pinspecs) cfg.append(gpiocfg.format(p.ADDR_WIDTH, p.DATA_WIDTH, - 0, # USERSPACE - bank, npins)) + 0, # USERSPACE + bank, npins)) cfg.append(muxcfg.format(p.ADDR_WIDTH, p.DATA_WIDTH, - 0, # USERSPACE - bank, npins)) + 0, # USERSPACE + bank, npins)) decl.append(gpiodec.format(npins, bank)) decl.append(muxdec .format(npins, bank)) idec.append(gpioifc.format(bank)) @@ -342,6 +341,6 @@ def write_bvp(bvp, p, ifaces): print dir(ifaces['gpioa']) print ifaces['gpioa'].pinspecs gpiodecl = '\n'.join(decl) + '\n' + '\n'.join(idec) - gpiocfg = '\n'.join(cfg) + gpiocfg = '\n'.join(cfg) bsv_file.write(axi4_lite.format(gpiodecl, gpiocfg)) # ################################################## diff --git a/src/myhdlgen/pinmux_generator.py b/src/myhdlgen/pinmux_generator.py index 9cf5bed..ddc6df2 100644 --- a/src/myhdlgen/pinmux_generator.py +++ b/src/myhdlgen/pinmux_generator.py @@ -24,7 +24,6 @@ def transfn(temp): return '_'.join(temp) - class IfPin(object): """ pin interface declaration. * name is the name of the pin @@ -94,6 +93,7 @@ class Interfaces(InterfacesBase): def __init__(self, pth=None): InterfacesBase.__init__(self, Interface, pth) + class MyHdlIface(object): def __init__(self, iface): self.pnames = [] diff --git a/src/myhdlgen/pins.py b/src/myhdlgen/pins.py index 9ee5575..28fcc2e 100644 --- a/src/myhdlgen/pins.py +++ b/src/myhdlgen/pins.py @@ -62,7 +62,7 @@ def test(testfn, clk, fncls, num_pins, num_fns, {0}): for pnum in range(npins): args.append("sel%d" % pnum) args.append("pin%d" % pnum) - #for pnum in range(nfns): + # for pnum in range(nfns): # args.append("fn%d" % pnum) args = ','.join(args) x = x.format(args) @@ -86,6 +86,7 @@ def proxy(func): return func(args[0], args[1], args[2], args[3]) return wrapper + class FnCls(object): def __init__(self): self.attrs = ['uart', 'i2c', 'spi', 'gpio'] @@ -96,6 +97,7 @@ class FnCls(object): def getfn(self, idx): return getattr(self, self.attrs[idx]) + @block def muxer(clk, p, ifaces, args): muxes = [] @@ -145,8 +147,8 @@ def test2(clk, fncls, num_pins, num_fns, args): inputs.append(fncls.i2c.out) inputs.append(fncls.spi.out) inputs.append(fncls.gpio.out) - #for i in range(4): - #inputs.append(fncls.getfn(i).out) + # for i in range(4): + # inputs.append(fncls.getfn(i).out) for i in range(len(muxes)): mux = muxes[i] @@ -266,8 +268,6 @@ def muxgen(fn, p, ifaces): mux_inst.convert(hdl="Verilog", initial_values=True, testbench=False) - - if __name__ == '__main__': fncls = FnCls() num_fns = 4 diff --git a/src/parse.py b/src/parse.py index 42886a6..b8efe82 100644 --- a/src/parse.py +++ b/src/parse.py @@ -14,8 +14,8 @@ class Parse(object): N_IO = 0 N_MUX_IO = 0 Addressing = 'WORD' - ADDR_WIDTH = 32 # TODO parameterise - DATA_WIDTH = 32 # TODO parameterise + ADDR_WIDTH = 32 # TODO parameterise + DATA_WIDTH = 32 # TODO parameterise # ================ # # Generating the number of bits for memory map # -- 2.30.2