From d8560bfbcb622ab6c056b996a6c1b580cd0f7ddc Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Fri, 27 Oct 2023 11:33:21 +0100 Subject: [PATCH] added english language description for lwzsux instruction --- openpower/isa/fixedloadshift.mdwn | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn index 7ace250a..903019cd 100644 --- a/openpower/isa/fixedloadshift.mdwn +++ b/openpower/isa/fixedloadshift.mdwn @@ -218,6 +218,19 @@ Pseudo-code: RT <- [0] * 32 || MEM(EA, 4) RA <- EA +Description: + + Let the effective address (EA) be the sum of the contents of + register RB shifted by (SH+1), and (RA). + + The word in storage addressed by EA is loaded into RT[32:63]. + RT[0:31] are set to 0. + + EA is placed into register RA. + + If RA=0 or RA=RT, the instruction form is invalid. + + Special Registers Altered: None -- 2.30.2