From d85e598a59f826d0fbd4af684c680b68970e6cda Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Mon, 21 Nov 2016 20:35:21 +0000 Subject: [PATCH] rs6000.md (movdi_internal32): Change constraints so that DImode can be allocated to FP/vector registers in... [gcc] 2016-11-21 Michael Meissner * config/rs6000/rs6000.md (movdi_internal32): Change constraints so that DImode can be allocated to FP/vector registers in more cases, and we can avoid direct move operations. If the register needs reloading, prefer GPRs over FP/vector registers. In the case of FPR vs. Altivec registers, prefer FPR registers unless we have the ISA 3.0 reg+offset scalar instructions. (movdi_internal64): Likewise. [gcc/testsuite] 2016-11-21 Michael Meissner * gcc.target/powerpc/ppc-round2.c: Allow XSCVDPSXWS and XSCVDPUXWS to be generated instead of FCTIWUZ or FCTIWZ. From-SVN: r242679 --- gcc/ChangeLog | 10 ++++++++++ gcc/config/rs6000/rs6000.md | 14 +++++++------- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/powerpc/ppc-round2.c | 4 ++-- 4 files changed, 24 insertions(+), 9 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9cb252625bf..842e8ff5f2c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2016-11-21 Michael Meissner + + * config/rs6000/rs6000.md (movdi_internal32): Change constraints + so that DImode can be allocated to FP/vector registers in more + cases, and we can avoid direct move operations. If the register + needs reloading, prefer GPRs over FP/vector registers. In the + case of FPR vs. Altivec registers, prefer FPR registers unless we + have the ISA 3.0 reg+offset scalar instructions. + (movdi_internal64): Likewise. + 2016-11-21 Jakub Jelinek PR middle-end/67335 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index acd4a7e508b..c932dac75a4 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8118,10 +8118,10 @@ (define_insn "*movdi_internal32" [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" - "=Y, r, r, ?m, ?*d, ?*d, - r, ?wY, ?Z, ?*wb, ?*wv, ?wi, - ?wo, ?wo, ?wv, ?wi, ?wi, ?wv, - ?wv") + "=Y, r, r, ^m, ^d, ^d, + r, ^wY, $Z, ^wb, $wv, ^wi, + *wo, *wo, *wv, *wi, *wi, *wv, + *wv") (match_operand:DI 1 "input_operand" "r, Y, r, d, m, d, @@ -8195,9 +8195,9 @@ (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" "=Y, r, r, r, r, r, - ?m, ?*d, ?*d, ?wY, ?Z, ?*wb, - ?*wv, ?wi, ?wo, ?wo, ?wv, ?wi, - ?wi, ?wv, ?wv, r, *h, *h, + ^m, ^d, ^d, ^Y, $Z, $wb, + $wv, ^wi, *wo, *wo, *wv, *wi, + *wi, *wv, *wv, r, *h, *h, ?*r, ?*wg, ?*r, ?*wj") (match_operand:DI 1 "input_operand" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index dd89d886503..cef6a277129 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-11-21 Michael Meissner + + * gcc.target/powerpc/ppc-round2.c: Allow XSCVDPSXWS and XSCVDPUXWS + to be generated instead of FCTIWUZ or FCTIWZ. + 2016-11-21 Jakub Jelinek PR middle-end/67335 diff --git a/gcc/testsuite/gcc.target/powerpc/ppc-round2.c b/gcc/testsuite/gcc.target/powerpc/ppc-round2.c index 39375a0e9d5..1890fca10be 100644 --- a/gcc/testsuite/gcc.target/powerpc/ppc-round2.c +++ b/gcc/testsuite/gcc.target/powerpc/ppc-round2.c @@ -5,8 +5,8 @@ /* { dg-options "-O2 -mcpu=power8" } */ /* { dg-final { scan-assembler-times "fcfid " 2 } } */ /* { dg-final { scan-assembler-times "fcfids " 2 } } */ -/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */ -/* { dg-final { scan-assembler-times "fctiwz " 2 } } */ +/* { dg-final { scan-assembler-times "fctiwuz \|xscvdpuxws " 2 } } */ +/* { dg-final { scan-assembler-times "fctiwz \|xscvdpsxws " 2 } } */ /* { dg-final { scan-assembler-times "mfvsrd " 4 } } */ /* { dg-final { scan-assembler-times "mtvsrwa " 2 } } */ /* { dg-final { scan-assembler-times "mtvsrwz " 2 } } */ -- 2.30.2