From d8612e6a30950eea9e2178c5828afcf989803654 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 31 Jul 2019 12:45:35 +0100 Subject: [PATCH] tidyup --- src/ieee754/fpadd/addstages.py | 2 +- src/ieee754/fpcommon/denorm.py | 66 ++++++++------------------- src/ieee754/fpcommon/postnormalise.py | 20 ++------ 3 files changed, 24 insertions(+), 64 deletions(-) diff --git a/src/ieee754/fpadd/addstages.py b/src/ieee754/fpadd/addstages.py index 76df0e87..48936583 100644 --- a/src/ieee754/fpadd/addstages.py +++ b/src/ieee754/fpadd/addstages.py @@ -10,13 +10,13 @@ from nmigen.cli import main, verilog from nmutil.singlepipe import StageChain from ieee754.pipeline import DynamicPipe -from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.denorm import FPSCData from ieee754.fpcommon.postcalc import FPAddStage1Data from ieee754.fpadd.align import FPAddAlignSingleMod from ieee754.fpadd.add0 import FPAddStage0Mod from ieee754.fpadd.add1 import FPAddStage1Mod + class FPAddAlignSingleAdd(DynamicPipe): def __init__(self, pspec): diff --git a/src/ieee754/fpcommon/denorm.py b/src/ieee754/fpcommon/denorm.py index 7cad0734..43e343ae 100644 --- a/src/ieee754/fpcommon/denorm.py +++ b/src/ieee754/fpcommon/denorm.py @@ -2,12 +2,13 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Module, Signal, Elaboratable +from nmigen import Module, Signal from nmigen.cli import main, verilog from math import log -from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPNumBaseRecord -from ieee754.fpcommon.fpbase import FPState, FPNumBase +from ieee754.fpcommon.modbase import FPModBase +from ieee754.fpcommon.fpbase import FPNumBaseRecord +from ieee754.fpcommon.fpbase import FPNumBase from ieee754.fpcommon.getop import FPPipeContext @@ -41,13 +42,11 @@ class FPSCData: return ret -class FPAddDeNormMod(FPState, Elaboratable): +class FPAddDeNormMod(FPModBase): def __init__(self, pspec, m_extra): - self.pspec = pspec self.m_extra = m_extra - self.i = self.ispec() - self.o = self.ospec() + super().__init__(pspec, "denormalise") def ispec(self): return FPSCData(self.pspec, self.m_extra) @@ -55,61 +54,32 @@ class FPAddDeNormMod(FPState, Elaboratable): def ospec(self): return FPSCData(self.pspec, self.m_extra) - def process(self, i): - return self.o - - def setup(self, m, i): - """ links module to inputs and outputs - """ - m.submodules.denormalise = self - m.d.comb += self.i.eq(i) - def elaborate(self, platform): m = Module() + comb = m.d.comb + m.submodules.denorm_in_a = in_a = FPNumBase(self.i.a) m.submodules.denorm_in_b = in_b = FPNumBase(self.i.b) - #m.submodules.denorm_out_a = self.o.a - #m.submodules.denorm_out_b = self.o.b - #m.submodules.denorm_out_z = self.o.z with m.If(~self.i.out_do_z): # XXX hmmm, don't like repeating identical code - m.d.comb += self.o.a.eq(self.i.a) + comb += self.o.a.eq(self.i.a) with m.If(in_a.exp_n127): - m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent + comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent with m.Else(): - m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit + comb += self.o.a.m[-1].eq(1) # set top mantissa bit - m.d.comb += self.o.b.eq(self.i.b) + comb += self.o.b.eq(self.i.b) with m.If(in_b.exp_n127): - m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent + comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent with m.Else(): - m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit + comb += self.o.b.m[-1].eq(1) # set top mantissa bit - m.d.comb += self.o.ctx.eq(self.i.ctx) - m.d.comb += self.o.z.eq(self.i.z) - m.d.comb += self.o.out_do_z.eq(self.i.out_do_z) - m.d.comb += self.o.oz.eq(self.i.oz) + comb += self.o.ctx.eq(self.i.ctx) + comb += self.o.z.eq(self.i.z) + comb += self.o.out_do_z.eq(self.i.out_do_z) + comb += self.o.oz.eq(self.i.oz) return m -class FPAddDeNorm(FPState): - - def __init__(self, width, id_wid): - FPState.__init__(self, "denormalise") - self.mod = FPAddDeNormMod(width) - self.out_a = FPNumBaseRecord(width) - self.out_b = FPNumBaseRecord(width) - - def setup(self, m, i): - """ links module to inputs and outputs - """ - self.mod.setup(m, i) - - m.d.sync += self.out_a.eq(self.mod.out_a) - m.d.sync += self.out_b.eq(self.mod.out_b) - - def action(self, m): - # Denormalised Number checks - m.next = "align" diff --git a/src/ieee754/fpcommon/postnormalise.py b/src/ieee754/fpcommon/postnormalise.py index 58afc4c7..653fdac2 100644 --- a/src/ieee754/fpcommon/postnormalise.py +++ b/src/ieee754/fpcommon/postnormalise.py @@ -2,17 +2,18 @@ # Copyright (C) Jonathan P Dawson 2013 # 2013-12-12 -from nmigen import Module, Signal, Cat, Mux, Elaboratable +from nmigen import Module, Signal, Cat, Mux from nmigen.cli import main, verilog from math import log +from ieee754.fpcommon.modbase import FPModBase from ieee754.fpcommon.fpbase import (Overflow, OverflowMod, FPNumBase, FPNumBaseRecord) from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.getop import FPPipeContext from ieee754.fpcommon.msbhigh import FPMSBHigh from ieee754.fpcommon.exphigh import FPEXPHigh -from .postcalc import FPAddStage1Data +from ieee754.fpcommon.postcalc import FPAddStage1Data class FPNorm1Data: @@ -32,13 +33,11 @@ class FPNorm1Data: return ret -class FPNorm1ModSingle(Elaboratable): +class FPNorm1ModSingle(FPModBase): def __init__(self, pspec, e_extra=False): - self.pspec = pspec self.e_extra = e_extra - self.i = self.ispec() - self.o = self.ospec() + super().__init__(pspec, "normalise_1") def ispec(self): return FPAddStage1Data(self.pspec, e_extra=self.e_extra) @@ -46,15 +45,6 @@ class FPNorm1ModSingle(Elaboratable): def ospec(self): return FPNorm1Data(self.pspec) - def setup(self, m, i): - """ links module to inputs and outputs - """ - m.submodules.normalise_1 = self - m.d.comb += self.i.eq(i) - - def process(self, i): - return self.o - def elaborate(self, platform): m = Module() -- 2.30.2