From d8740be15930b820ab51d7a76695194022a83551 Mon Sep 17 00:00:00 2001 From: "Jose E. Marchesi" Date: Thu, 4 Jun 2020 16:17:07 +0200 Subject: [PATCH] cpu,gas,opcodes: remove no longer needed workaround from the BPF port cpu/ChangeLog: 2020-06-02 Jose E. Marchesi * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64. * bpf.opc (bpf_print_insn): Do not set endian_code here. gas/ChangeLog: 2020-06-04 Jose E. Marchesi * config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to bpf_cgen_cpu_open. (md_assemble): Remove no longer needed hack. opcodes/ChangeLog: 2020-06-04 Jose E. Marchesi * disassemble.c (disassemble_init_for_target): Set endian_code for bpf targets. * bpf-desc.c: Regenerate. * bpf-opc.c: Likewise. * bpf-dis.c: Likewise. --- cpu/ChangeLog | 5 +++++ cpu/bpf.cpu | 10 +++------ cpu/bpf.opc | 1 - gas/ChangeLog | 6 ++++++ gas/config/tc-bpf.c | 6 ++---- opcodes/ChangeLog | 8 ++++++++ opcodes/bpf-desc.c | 4 ++-- opcodes/bpf-dis.c | 1 - opcodes/bpf-opc.c | 48 +++++++++++++++++++++---------------------- opcodes/disassemble.c | 1 + 10 files changed, 51 insertions(+), 39 deletions(-) diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 41ff1812342..f2ac243c68e 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,8 @@ +2020-06-02 Jose E. Marchesi + + * bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64. + * bpf.opc (bpf_print_insn): Do not set endian_code here. + 2020-06-02 Jose E. Marchesi * mep.opc (print_slot_insn): Pass the insn endianness to diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu index 47d7cb0f158..dcfb0ca8cf1 100644 --- a/cpu/bpf.cpu +++ b/cpu/bpf.cpu @@ -98,13 +98,9 @@ ;; Length of an unknown instruction. Used by disassembly and by the ;; simulator's invalid insn handler. (default-insn-bitsize 64) - ;; Number of bits of insn that can be initially fetched. XXX this - ;; should be 64 (the size of the smallest insn) but until CGEN - ;; gets fixed to place constant fields in their own words, we have - ;; to use this workaround to avoid the opcode byte to be placed at - ;; the wrong side of the instruction when assembling in - ;; big-endian. - (base-insn-bitsize 8))) + ;; Number of bits of insn that can be initially fetched. This is + ;; the size of the smallest insn. + (base-insn-bitsize 64))) (define-bpf-isa le) (define-bpf-isa be) diff --git a/cpu/bpf.opc b/cpu/bpf.opc index e2acaa4341c..e70ee04841d 100644 --- a/cpu/bpf.opc +++ b/cpu/bpf.opc @@ -129,7 +129,6 @@ bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) info->bytes_per_chunk = 1; info->bytes_per_line = 8; - info->endian_code = BFD_ENDIAN_BIG; /* Attempt to read the base part of the insn. */ buflen = cd->base_insn_bitsize / 8; diff --git a/gas/ChangeLog b/gas/ChangeLog index bb917ccc70e..91e3dc2ba25 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,9 @@ +2020-06-04 Jose E. Marchesi + + * config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to + bpf_cgen_cpu_open. + (md_assemble): Remove no longer needed hack. + 2020-06-04 Jose E. Marchesi * cgen.c (gas_cgen_finish_insn): Pass the endianness to diff --git a/gas/config/tc-bpf.c b/gas/config/tc-bpf.c index 7c7d22e4776..b742f426a1f 100644 --- a/gas/config/tc-bpf.c +++ b/gas/config/tc-bpf.c @@ -174,6 +174,8 @@ md_begin (void) gas_cgen_cpu_desc = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ENDIAN, target_big_endian ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE, + CGEN_CPU_OPEN_INSN_ENDIAN, + CGEN_ENDIAN_LITTLE, CGEN_CPU_OPEN_ISAS, bpf_isa, CGEN_CPU_OPEN_END); @@ -354,10 +356,6 @@ md_assemble (char *str) CGEN_INSN_INT buffer[CGEN_MAX_INSN_SIZE / sizeof (CGEN_INT_INSN_P)]; #else unsigned char buffer[CGEN_MAX_INSN_SIZE]; - memset (buffer, 0, CGEN_MAX_INSN_SIZE); /* XXX to remove when CGEN - is fixed to handle - opcodes-in-words - properly. */ #endif gas_cgen_init_parse (); diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 39df27efd71..63824c8e336 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2020-06-04 Jose E. Marchesi + + * disassemble.c (disassemble_init_for_target): Set endian_code for + bpf targets. + * bpf-desc.c: Regenerate. + * bpf-opc.c: Likewise. + * bpf-dis.c: Likewise. + 2020-06-03 Jose E. Marchesi * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. diff --git a/opcodes/bpf-desc.c b/opcodes/bpf-desc.c index abd8c41006f..6319f100f3c 100644 --- a/opcodes/bpf-desc.c +++ b/opcodes/bpf-desc.c @@ -119,8 +119,8 @@ const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[] = /* Instruction set variants. */ static const CGEN_ISA bpf_cgen_isa_table[] = { - { "ebpfle", 64, 8, 64, 128 }, - { "ebpfbe", 64, 8, 64, 128 }, + { "ebpfle", 64, 64, 64, 128 }, + { "ebpfbe", 64, 64, 64, 128 }, { 0, 0, 0, 0, 0 } }; diff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c index 4d01112d25f..9425ee7f3cb 100644 --- a/opcodes/bpf-dis.c +++ b/opcodes/bpf-dis.c @@ -75,7 +75,6 @@ bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) info->bytes_per_chunk = 1; info->bytes_per_line = 8; - info->endian_code = BFD_ENDIAN_BIG; /* Attempt to read the base part of the insn. */ buflen = cd->base_insn_bitsize / 8; diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c index 3ecd35d8bce..00f3b25f768 100644 --- a/opcodes/bpf-opc.c +++ b/opcodes/bpf-opc.c @@ -50,99 +50,99 @@ static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { }; static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED = { - 8, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED = { - 8, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ldabsw ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ldindwle ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ldindwbe ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_callle ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED = { - 8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } + 64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } } }; #undef F diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 25816efb56c..299c23db137 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -660,6 +660,7 @@ disassemble_init_for_target (struct disassemble_info * info) #endif #ifdef ARCH_bpf case bfd_arch_bpf: + info->endian_code = BFD_ENDIAN_LITTLE; if (!info->private_data) { info->private_data = cgen_bitset_create (ISA_EBPFMAX); -- 2.30.2