From d878e79bf80f4c7bb0c6dd827e4c4dd37c5385bf Mon Sep 17 00:00:00 2001 From: "H.J. Lu" Date: Thu, 1 Oct 2015 13:34:49 +0000 Subject: [PATCH] Enable bt and and movzx for Lakemont * config/i386/x86-tune.def (X86_TUNE_USE_BT): Enable for Lakemont. (X86_TUNE_ZERO_EXTEND_WITH_AND): Disable for Lakemont. From-SVN: r228337 --- gcc/ChangeLog | 6 ++++++ gcc/config/i386/x86-tune.def | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2d86889bd5a..70f964617b3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-10-01 H.J. Lu + + * config/i386/x86-tune.def (X86_TUNE_USE_BT): Enable for + Lakemont. + (X86_TUNE_ZERO_EXTEND_WITH_AND): Disable for Lakemont. + 2015-10-01 James Greenhalgh * config/arm/aarch-common-protos.h diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 3b3f14911cc..213c604bc79 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -292,7 +292,7 @@ DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd", /* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */ DEF_TUNE (X86_TUNE_USE_BT, "use_bt", m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL - | m_AMD_MULTIPLE | m_GENERIC) + | m_LAKEMONT | m_AMD_MULTIPLE | m_GENERIC) /*****************************************************************************/ /* 387 instruction selection tuning */ @@ -448,7 +448,7 @@ DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486) /* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead of mozbl/movwl. */ DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and", - m_486 | m_PENT | m_LAKEMONT) + m_486 | m_PENT) /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode and SImode multiply, but 386 and 486 do HImode multiply faster. */ -- 2.30.2