From d88a7c1700397abab309250bdbb8ceadb1cbc249 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Sep 2018 05:35:10 +0100 Subject: [PATCH] assign SV REG CSRs (using new union ability) --- riscv/processor.cc | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/riscv/processor.cc b/riscv/processor.cc index 0ad4e3e..7d95c49 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -354,7 +354,26 @@ void processor_t::set_csr(int which, reg_t val) case CSR_SVREGCFG5: case CSR_SVREGCFG6: case CSR_SVREGCFG7: + { + // identify which (pair) of SV config CAM registers are being set + int tbidx = (which - CSR_SVREGCFG0) * 2; + // lower 16 bits go into even, upper into odd... + state.sv_csrs[tbidx].u = get_field(val, 0xffff); + state.sv_csrs[tbidx+1].u = get_field(val, 0xffff0000); + // clear out all CSRs above the one(s) being set: this ensures that + // when it comes to context-switching, it's clear what needs to be saved + for (int i = tbidx+2; i < 16; i++) + { + state.sv_csrs[i].u = 0; + } + // okaaay and now "unpack" the CAM to make it easier to use. this + // approach is not designed to be efficient right now. optimise later + for (int i = 0; i < SV_CSR_SZ; i++) + { + // TODO + } break; + } #endif case CSR_FFLAGS: dirty_fp_state; -- 2.30.2