From d893f8d85a9fdb5c9c2601d77ac115bb147f5abe Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 22 Jul 2019 09:47:36 +0100 Subject: [PATCH] config/setup/imports --- src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py | 20 +++++++++----------- src/ieee754/fpdiv/div2.py | 3 ++- src/ieee754/fpdiv/divstages.py | 4 ++-- src/ieee754/fpdiv/pipeline.py | 11 ++++++++--- 4 files changed, 21 insertions(+), 17 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py index 9e1541fd..a885ae04 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py @@ -122,17 +122,12 @@ class DivPipeBaseStage: m.d.comb += self.o.out_do_z.eq(self.i.out_do_z) m.d.comb += self.o.ctx.eq(self.i.ctx) - def get_core_config(self): - m_width = self.pspec.m_width # mantissa width - # 4 extra bits on the mantissa: MSB is zero, MSB-1 is 1 - # then there is guard and round at the LSB end - return DivPipeCoreConfig(m_width+4, 0, log_radix=2) - class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage): def __init__(self, pspec): self.pspec = pspec + print ("DivPipeSetupStage", pspec, pspec.core_config) DivPipeCoreSetupStage.__init__(self, pspec.core_config) def ispec(self): @@ -144,7 +139,8 @@ class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage): return DivPipeInterstageData(self.pspec) def elaborate(self, platform): - m = DivPipeCoreSetupStage(platform) # XXX TODO: out_do_z logic! + # XXX TODO: out_do_z logic! + m = DivPipeCoreSetupStage.elaborate(self, platform) self._elaborate(m, platform) return m @@ -164,16 +160,17 @@ class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage): return DivPipeInterstageData(self.pspec) def elaborate(self, platform): - m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic! + # XXX TODO: out_do_z logic! + m = DivPipeCoreCalculateStage.elaborate(self, platform) self._elaborate(m, platform) return m class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage): - def __init__(self, pspec, stage_index): + def __init__(self, pspec): self.pspec = pspec - DivPipeCoreFinalStage.__init__(self, pspec.core_config, stage_index) + DivPipeCoreFinalStage.__init__(self, pspec.core_config) def ispec(self): """ Get the input spec for this pipeline stage.""" @@ -184,7 +181,8 @@ class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage): return DivPipeOutputData(self.pspec) def elaborate(self, platform): - m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic! + # XXX TODO: out_do_z logic! + m = DivPipeCoreFinalStage.elaborate(self, platform) self._elaborate(m, platform) return m diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py index a92043c3..61c7fa4c 100644 --- a/src/ieee754/fpdiv/div2.py +++ b/src/ieee754/fpdiv/div2.py @@ -3,11 +3,12 @@ Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99 """ -from nmigen import Module, Signal, Elaboratable +from nmigen import Module, Signal, Elaboratable, Cat from nmigen.cli import main, verilog from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.postcalc import FPAddStage1Data +from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeOutputData class FPDivStage2Mod(FPState, Elaboratable): diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py index 385743f8..112c9d88 100644 --- a/src/ieee754/fpdiv/divstages.py +++ b/src/ieee754/fpdiv/divstages.py @@ -162,10 +162,10 @@ class FPDivStagesFinal(FPState, SimpleHandshake): # will add. for count in range(self.n_stages): # number of combinatorial stages idx = count + self.stage_offs - divstages.append(DivPipeCalculateStage(pspec, idx)) + divstages.append(DivPipeCalculateStage(self.pspec, idx)) # does the final conversion from intermediary to output data - divstages.append(DivPipeFinalStage(pspec)) + divstages.append(DivPipeFinalStage(self.pspec)) # does conversion from DivPipeOutputData into # FPAddStage1Data format (bad name, TODO, doesn't matter), diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py index 13cac17b..1c137a82 100644 --- a/src/ieee754/fpdiv/pipeline.py +++ b/src/ieee754/fpdiv/pipeline.py @@ -81,8 +81,8 @@ class FPDIVBasePipe(ControlBase): ControlBase.__init__(self) pipechain = [] - n_stages = 6 # TODO (depends on width) - n_comb_stages = 3 # TODO (depends on how many RS's we want) + max_n_comb_stages = 2 # TODO (depends on how many RS's we want) + n_stages = pspec.fpformat.m_width // max_n_comb_stages stage_idx = 0 # to which the answer: "as few as possible" # is required. too many ReservationStations @@ -90,6 +90,7 @@ class FPDIVBasePipe(ControlBase): for i in range(n_stages): + n_comb_stages = max_n_comb_stages # needs to convert input from pipestart ospec if i == 0: kls = FPDivStagesSetup @@ -151,7 +152,11 @@ class FPDIVMuxInOut(ReservationStations): # (used in DivPipeBaseStage.get_core_config) fpformat = FPFormat.standard(width) log2_radix = 2 - cfg = DivPipeCoreConfig(width, fpformat.fraction_width, log2_radix) + + # 4 extra bits on the mantissa: MSB is zero, MSB-1 is 1 + # then there is guard and round at the LSB end + cfg = DivPipeCoreConfig(width+4, fpformat.fraction_width, log2_radix) + self.pspec.fpformat = fpformat self.pspec.log2_radix = log2_radix self.pspec.core_config = cfg -- 2.30.2