From d8943f8852b65101ca6e495a386d68b6dec98be6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 4 Dec 2021 17:46:23 +0000 Subject: [PATCH] test in SimState for access to RADIX memory, bypass and get contents direct --- src/openpower/test/state.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py index 77e881c2..ee884f81 100644 --- a/src/openpower/test/state.py +++ b/src/openpower/test/state.py @@ -23,6 +23,7 @@ methods, the use of yield from/yield is required. from openpower.decoder.power_enums import XER_bits +from openpower.decoder.isa.radixmmu import RADIX from openpower.util import log import os import sys @@ -216,12 +217,15 @@ class SimState(State): def get_mem(self): if False: yield - keys = list(self.sim.mem.mem.keys()) + mem = self.sim.mem + if isinstance(mem, RADIX): + mem = mem.mem + keys = list(mem.mem.keys()) self.mem = {} # from each address in the underlying mem-simulated dictionary # issue a 64-bit LD (with no byte-swapping) for k in keys: - data = self.sim.mem.ld(k*8, 8, False) + data = mem.ld(k*8, 8, False) self.mem[k*8] = data -- 2.30.2