From d8a96934874e0a4a707471c7770e90589fce33eb Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 13:54:12 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 0e4082c8d..4d8f5a817 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -552,8 +552,9 @@ The similarity to ZOLC should not have gone unnoticed: where ZOLC has nested conditional for-loops Extra-V appears to have just the one conditional for-loop, but the key strategically-crucial part of this multi-faceted puzzle is that due to the deterministic and -coherent nature of Extra-V, the processing of the loops is -*embedded right next to the memory* +coherent nature of Extra-V, the processing of the loops is not +done close to the CPU it is +*embedded right next to the memory*. **Snitch** -- 2.30.2