From d8b26bc6092501585d3e9533c8d34b2fb9ed996e Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sat, 16 May 2020 13:35:22 -0400 Subject: [PATCH] Minor cleanup --- src/soc/cr/main_stage.py | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/soc/cr/main_stage.py b/src/soc/cr/main_stage.py index 21f19b65..4a27fcd4 100644 --- a/src/soc/cr/main_stage.py +++ b/src/soc/cr/main_stage.py @@ -8,9 +8,7 @@ from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array) from nmutil.pipemodbase import PipeModBase from soc.cr.pipe_data import CRInputData, CROutputData -from ieee754.part.partsig import PartitionedSignal from soc.decoder.power_enums import InternalOp -from soc.countzero.countzero import ZeroCounter from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange @@ -57,7 +55,6 @@ class CRMainStage(PipeModBase): comb += cr_output[31-i].eq(cr_out_arr[i]) comb += cr_out_arr[i].eq(cr_arr[i]) - # crand/cror and friends get decoded to the same opcode, but # one of the fields inside the instruction is a 4 bit lookup # table. This lookup table gets indexed by bits a and b from @@ -68,7 +65,6 @@ class CRMainStage(PipeModBase): # There's no field, just have to grab it directly from the insn comb += lut.eq(self.i.ctx.op.insn[6:10]) - with m.Switch(op.insn_type): with m.Case(InternalOp.OP_MCRF): # MCRF copies the 4 bits of crA to crB (for instance @@ -116,11 +112,9 @@ class CRMainStage(PipeModBase): for i in range(8): comb += mask[i*4:(i+1)*4].eq(Repl(fxm[i], 4)) - - comb += cr_output.eq((self.i.a[0:32] & mask) | - (self.i.cr & ~mask)) - + comb += cr_output.eq((self.i.a[0:32] & mask) | + (self.i.cr & ~mask)) comb += self.o.cr.eq(cr_output) comb += self.o.ctx.eq(self.i.ctx) -- 2.30.2