From d8bd4123fb04d605ea6bb0c46b129dae6fac9a05 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 6 Nov 2018 10:59:38 +0000
Subject: [PATCH] mention shape/remap

---
 3d_gpu/microarchitecture.mdwn | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index 92e614c22..e6118d4cc 100644
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -14,7 +14,7 @@
   TODO: consider 2R for registers to be used as predication targets
   if >= 32.
 * Potentially: Lane-swapping / crossing / data-multiplexing
-  bus on register data
+  bus on register data (particularly because of SHAPE-REMAP (1D/2D/3D)
 * Potentially: Registers subdivided into 16-bit, to match
   elwidth down to 16-bit (for FP16).  8-bit elwidth only
   goes down as far as twin-SIMD (with predication).  This
-- 
2.30.2