From d8c345b5086662cba2518e608c550718efdabf66 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 25 Jun 2020 20:25:13 +0100 Subject: [PATCH] add beginnings of Pi2LSUI --- src/soc/experiment/pi2ls.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py index 7b2e6d07..ac2936bb 100644 --- a/src/soc/experiment/pi2ls.py +++ b/src/soc/experiment/pi2ls.py @@ -19,3 +19,17 @@ st.data/64 x_st_data_i st.ok/1 probably kinda redundant, set to x_st_i """ + +from soc.minerva.units.loadstore import LoadStoreUnitInterface +from soc.experiment.pimem import PortInterface +from nmigen import Elaboratable, Module, Signal + +class Pi2LSUI(Elaboratable): + + def __init__(self, name, regwid=64, addrwid=48): + self.pi = PortInterface(name="%s_pi", regwid, addrwid) + self.lsui = LoadStoreUnitInterface(addrwid, 4, regwid) + + def elaborate(self, platform): + m = Module() + return m -- 2.30.2