From d8c69a9281025fd57590799c70c4d96158b748e6 Mon Sep 17 00:00:00 2001 From: Ian Caulfield Date: Tue, 2 Apr 2013 11:25:50 +0000 Subject: [PATCH] Add support for Cortex-A53. 2013-04-02 Ian Caulfield Ramana Radhakrishnan * config/arm/arm-arches.def (armv8-a): Default to cortex-a53. * config/arm/t-arm (MD_INCLUDES): Depend on cortex-a53.md. * config/arm/cortex-a53.md: New file. * config/arm/bpabi.h (BE8_LINK_SPEC): Handle cortex-a53. * config/arm/arm.md (generic_sched, generic_vfp): Handle cortex-a53. * config/arm/arm.c (arm_issue_rate): Likewise. * config/arm/arm-tune.md: Regenerate * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-cores.def: Add cortex-a53. From-SVN: r197346 --- gcc/ChangeLog | 17 +- gcc/config/arm/arm-arches.def | 2 +- gcc/config/arm/arm-cores.def | 1 + gcc/config/arm/arm-tables.opt | 3 + gcc/config/arm/arm-tune.md | 2 +- gcc/config/arm/arm.c | 1 + gcc/config/arm/arm.md | 5 +- gcc/config/arm/bpabi.h | 2 + gcc/config/arm/cortex-a53.md | 296 ++++++++++++++++++++++++++++++++++ gcc/config/arm/t-arm | 1 + 10 files changed, 324 insertions(+), 6 deletions(-) create mode 100644 gcc/config/arm/cortex-a53.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index be3b818d77f..f7155c0f4af 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2013-04-02 Ian Caulfield + Ramana Radhakrishnan + + * config/arm/arm-arches.def (armv8-a): Default to cortex-a53. + * config/arm/t-arm (MD_INCLUDES): Depend on cortex-a53.md. + * config/arm/cortex-a53.md: New file. + * config/arm/bpabi.h (BE8_LINK_SPEC): Handle cortex-a53. + * config/arm/arm.md (generic_sched, generic_vfp): Handle cortex-a53. + * config/arm/arm.c (arm_issue_rate): Likewise. + * config/arm/arm-tune.md: Regenerate + * config/arm/arm-tables.opt: Regenerate. + * config/arm/arm-cores.def: Add cortex-a53. + 2013-04-02 Zhenqiang Chen * config/arm/uclinux-elf.h: Add %L to LINK_GCC_C_SEQUENCE_SPEC for @@ -5,8 +18,8 @@ 2013-04-02 Sofiane Naci - * config/aarch64/aarch64.md (*mov_aarch64): Add variants for scalar - load/store operations using B/H registers. + * config/aarch64/aarch64.md (*mov_aarch64): Add variants for + scalar load/store operations using B/H registers. (*zero_extend2_aarch64): Likewise. 2013-04-02 Sofiane Naci diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def index 613163081ca..fcf34012262 100644 --- a/gcc/config/arm/arm-arches.def +++ b/gcc/config/arm/arm-arches.def @@ -53,6 +53,6 @@ ARM_ARCH("armv7-a", cortexa8, 7A, FL_CO_PROC | FL_FOR_ARCH7A) ARM_ARCH("armv7-r", cortexr4, 7R, FL_CO_PROC | FL_FOR_ARCH7R) ARM_ARCH("armv7-m", cortexm3, 7M, FL_CO_PROC | FL_FOR_ARCH7M) ARM_ARCH("armv7e-m", cortexm4, 7EM, FL_CO_PROC | FL_FOR_ARCH7EM) -ARM_ARCH("armv8-a", cortexa15, 8A, FL_CO_PROC | FL_FOR_ARCH8A) +ARM_ARCH("armv8-a", cortexa53, 8A, FL_CO_PROC | FL_FOR_ARCH8A) ARM_ARCH("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT) ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2) diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 185f78e7b00..3d59fa6f5a9 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -129,6 +129,7 @@ ARM_CORE("cortex-a7", cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex) ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15) +ARM_CORE("cortex-a53", cortexa53, 8A, FL_LDSCHED, cortex_a5) ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index ad52d18915d..bf206959569 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -249,6 +249,9 @@ Enum(processor_type) String(cortex-a9) Value(cortexa9) EnumValue Enum(processor_type) String(cortex-a15) Value(cortexa15) +EnumValue +Enum(processor_type) String(cortex-a53) Value(cortexa53) + EnumValue Enum(processor_type) String(cortex-r4) Value(cortexr4) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index ac85f94b3fd..e4da0988b22 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from arm-cores.def (define_attr "tune" - "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexr7,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4" + "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexa53,cortexr4,cortexr4f,cortexr5,cortexr7,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 88165f27da4..fe6902f2225 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -25873,6 +25873,7 @@ arm_issue_rate (void) case cortexa7: case cortexa8: case cortexa9: + case cortexa53: case fa726te: case marvell_pj4: return 2; diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 8895080cb03..d5fcd505178 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -496,7 +496,7 @@ (define_attr "generic_sched" "yes,no" (const (if_then_else - (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexm4,marvell_pj4") + (ior (eq_attr "tune" "fa526,fa626,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexa53,cortexm4,marvell_pj4") (eq_attr "tune_cortexr4" "yes")) (const_string "no") (const_string "yes")))) @@ -504,7 +504,7 @@ (define_attr "generic_vfp" "yes,no" (const (if_then_else (and (eq_attr "fpu" "vfp") - (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,cortexa8,cortexa9,cortexm4,marvell_pj4") + (eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa7,cortexa8,cortexa9,cortexa53,cortexm4,marvell_pj4") (eq_attr "tune_cortexr4" "no")) (const_string "yes") (const_string "no")))) @@ -525,6 +525,7 @@ (include "cortex-a8.md") (include "cortex-a9.md") (include "cortex-a15.md") +(include "cortex-a53.md") (include "cortex-r4.md") (include "cortex-r4f.md") (include "cortex-m4.md") diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index bee429f82db..8e6683b3b23 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -60,6 +60,7 @@ |mcpu=cortex-a7 \ |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \ |mcpu=marvell-pj4 \ + |mcpu=cortex-a53 \ |mcpu=generic-armv7-a \ |march=armv7-m|mcpu=cortex-m3 \ |march=armv7e-m|mcpu=cortex-m4 \ @@ -71,6 +72,7 @@ " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5 \ |mcpu=cortex-a7 \ |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \ + |mcpu=cortex-a53 \ |mcpu=marvell-pj4 \ |mcpu=generic-armv7-a \ |march=armv7-m|mcpu=cortex-m3 \ diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md new file mode 100644 index 00000000000..b6a291e017b --- /dev/null +++ b/gcc/config/arm/cortex-a53.md @@ -0,0 +1,296 @@ +;; ARM Cortex-A53 pipeline description +;; Copyright (C) 2013 Free Software Foundation, Inc. +;; +;; Contributed by ARM Ltd. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. +;; +;; GCC is distributed in the hope that it will be useful, but +;; WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +;; General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_automaton "cortex_a53") + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; Functional units. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; There are two main integer execution pipelines, described as +;; slot 0 and issue slot 1. + +(define_cpu_unit "cortex_a53_slot0" "cortex_a53") +(define_cpu_unit "cortex_a53_slot1" "cortex_a53") + +(define_reservation "cortex_a53_slot_any" "cortex_a53_slot0|cortex_a53_slot1") +(define_reservation "cortex_a53_single_issue" "cortex_a53_slot0+cortex_a53_slot1") + +;; The load/store pipeline. Load/store instructions can dual-issue from +;; either pipeline, but two load/stores cannot simultaneously issue. + +(define_cpu_unit "cortex_a53_ls" "cortex_a53") + +;; The store pipeline. Shared between both execution pipelines. + +(define_cpu_unit "cortex_a53_store" "cortex_a53") + +;; The branch pipeline. Branches can dual-issue with other instructions +;; (except when those instructions take multiple cycles to issue). + +(define_cpu_unit "cortex_a53_branch" "cortex_a53") + +;; The integer divider. + +(define_cpu_unit "cortex_a53_idiv" "cortex_a53") + +;; The floating-point add pipeline used to model the usage +;; of the add pipeline by fmac instructions. + +(define_cpu_unit "cortex_a53_fpadd_pipe" "cortex_a53") + +;; Floating-point div/sqrt (long latency, out-of-order completion). + +(define_cpu_unit "cortex_a53_fp_div_sqrt" "cortex_a53") + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; ALU instructions. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_insn_reservation "cortex_a53_alu" 2 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "alu_reg,simple_alu_imm")) + "cortex_a53_slot_any") + +(define_insn_reservation "cortex_a53_alu_shift" 2 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "alu_shift,alu_shift_reg")) + "cortex_a53_slot_any") + +;; Forwarding path for unshifted operands. + +(define_bypass 1 "cortex_a53_alu,cortex_a53_alu_shift" + "cortex_a53_alu") + +(define_bypass 1 "cortex_a53_alu,cortex_a53_alu_shift" + "cortex_a53_alu_shift" + "arm_no_early_alu_shift_dep") + +;; The multiplier pipeline can forward results so there's no need to specify +;; bypasses. Multiplies can only single-issue currently. + +(define_insn_reservation "cortex_a53_mul" 3 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "mult")) + "cortex_a53_single_issue") + +;; A multiply with a single-register result or an MLA, followed by an +;; MLA with an accumulator dependency, has its result forwarded so two +;; such instructions can issue back-to-back. + +(define_bypass 1 "cortex_a53_mul" + "cortex_a53_mul" + "arm_mac_accumulator_is_mul_result") + +;; Punt with a high enough latency for divides. +(define_insn_reservation "cortex_a53_udiv" 8 + (and (eq_attr "tune" "cortexa53") + (eq_attr "insn" "udiv")) + "(cortex_a53_slot0+cortex_a53_idiv),cortex_a53_idiv*7") + +(define_insn_reservation "cortex_a53_sdiv" 9 + (and (eq_attr "tune" "cortexa53") + (eq_attr "insn" "sdiv")) + "(cortex_a53_slot0+cortex_a53_idiv),cortex_a53_idiv*8") + + +(define_bypass 2 "cortex_a53_mul,cortex_a53_udiv,cortex_a53_sdiv" + "cortex_a53_alu") +(define_bypass 2 "cortex_a53_mul,cortex_a53_udiv,cortex_a53_sdiv" + "cortex_a53_alu_shift" + "arm_no_early_alu_shift_dep") + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; Load/store instructions. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; Address-generation happens in the issue stage. + +(define_insn_reservation "cortex_a53_load1" 3 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "load_byte,load1")) + "cortex_a53_slot_any+cortex_a53_ls") + +(define_insn_reservation "cortex_a53_store1" 2 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "store1")) + "cortex_a53_slot_any+cortex_a53_ls+cortex_a53_store") + +(define_insn_reservation "cortex_a53_load2" 3 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "load2")) + "cortex_a53_single_issue+cortex_a53_ls") + +(define_insn_reservation "cortex_a53_store2" 2 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "store2")) + "cortex_a53_single_issue+cortex_a53_ls+cortex_a53_store") + +(define_insn_reservation "cortex_a53_load3plus" 4 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "load3,load4")) + "(cortex_a53_single_issue+cortex_a53_ls)*2") + +(define_insn_reservation "cortex_a53_store3plus" 3 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "store3,store4")) + "(cortex_a53_single_issue+cortex_a53_ls+cortex_a53_store)*2") + +;; Load/store addresses are required early in Issue. +(define_bypass 3 "cortex_a53_load1,cortex_a53_load2,cortex_a53_load3plus,cortex_a53_alu,cortex_a53_alu_shift" + "cortex_a53_load*" + "arm_early_load_addr_dep") +(define_bypass 3 "cortex_a53_load1,cortex_a53_load2,cortex_a53_load3plus,cortex_a53_alu,cortex_a53_alu_shift" + "cortex_a53_store*" + "arm_early_store_addr_dep") + +;; Load data can forward in the ALU pipeline +(define_bypass 2 "cortex_a53_load1,cortex_a53_load2" + "cortex_a53_alu") +(define_bypass 2 "cortex_a53_load1,cortex_a53_load2" + "cortex_a53_alu_shift" + "arm_no_early_alu_shift_dep") + +;; ALU ops can forward to stores. +(define_bypass 0 "cortex_a53_alu,cortex_a53_alu_shift" + "cortex_a53_store1,cortex_a53_store2,cortex_a53_store3plus" + "arm_no_early_store_addr_dep") + +(define_bypass 1 "cortex_a53_mul,cortex_a53_udiv,cortex_a53_sdiv,cortex_a53_load1,cortex_a53_load2,cortex_a53_load3plus" + "cortex_a53_store1,cortex_a53_store2,cortex_a53_store3plus" + "arm_no_early_store_addr_dep") + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; Branches. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; Currently models all branches as dual-issuable from either execution +;; slot, which isn't true for all cases. We still need to model indirect +;; branches. + +(define_insn_reservation "cortex_a53_branch" 0 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "branch,call")) + "cortex_a53_slot_any+cortex_a53_branch") + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; Floating-point arithmetic. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_insn_reservation "cortex_a53_fpalu" 4 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ + fcmps, fcmpd")) + "cortex_a53_slot0+cortex_a53_fpadd_pipe") + +(define_insn_reservation "cortex_a53_fconst" 2 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "fconsts,fconstd")) + "cortex_a53_slot0+cortex_a53_fpadd_pipe") + +(define_insn_reservation "cortex_a53_fpmul" 4 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "fmuls,fmuld")) + "cortex_a53_slot0") + +;; For single-precision multiply-accumulate, the add (accumulate) is issued after +;; the multiply completes. Model that accordingly. + +(define_insn_reservation "cortex_a53_fpmac" 8 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "fmacs,fmacd,ffmas,ffmad")) + "cortex_a53_slot0, nothing*3, cortex_a53_fpadd_pipe") + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; Floating-point divide/square root instructions. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; fsqrt really takes one cycle less, but that is not modelled. + +(define_insn_reservation "cortex_a53_fdivs" 14 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "fdivs")) + "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 13") + +(define_insn_reservation "cortex_a53_fdivd" 29 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "fdivd")) + "cortex_a53_slot0, cortex_a53_fp_div_sqrt * 28") + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; VFP to/from core transfers. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_insn_reservation "cortex_a53_r2f" 4 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "r_2_f")) + "cortex_a53_slot0") + +(define_insn_reservation "cortex_a53_f2r" 2 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "f_2_r")) + "cortex_a53_slot0") + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; VFP flag transfer. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_insn_reservation "cortex_a53_f_flags" 4 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "f_flag")) + "cortex_a53_slot0") + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; VFP load/store. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +(define_insn_reservation "cortex_a53_f_loads" 4 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "f_loads")) + "cortex_a53_slot0") + +(define_insn_reservation "cortex_a53_f_loadd" 5 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "f_loadd")) + "cortex_a53_slot0") + +(define_insn_reservation "cortex_a53_f_stores" 0 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "f_stores")) + "cortex_a53_slot0") + +(define_insn_reservation "cortex_a53_f_stored" 0 + (and (eq_attr "tune" "cortexa53") + (eq_attr "type" "f_stored")) + "cortex_a53_slot0") + +;; Load-to-use for floating-point values has a penalty of one cycle, +;; i.e. a latency of two. + +(define_bypass 2 "cortex_a53_f_loads" + "cortex_a53_fpalu, cortex_a53_fpmac, cortex_a53_fpmul,\ + cortex_a53_fdivs, cortex_a53_fdivd,\ + cortex_a53_f2r") + +(define_bypass 2 "cortex_a53_f_loadd" + "cortex_a53_fpalu, cortex_a53_fpmac, cortex_a53_fpmul,\ + cortex_a53_fdivs, cortex_a53_fdivd,\ + cortex_a53_f2r") + diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index 96b88de0f7c..79d8e74a182 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -39,6 +39,7 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \ $(srcdir)/config/arm/cortex-a8-neon.md \ $(srcdir)/config/arm/cortex-a9.md \ $(srcdir)/config/arm/cortex-a9-neon.md \ + $(srcdir)/config/arm/cortex-a53.md \ $(srcdir)/config/arm/cortex-m4-fpu.md \ $(srcdir)/config/arm/cortex-m4.md \ $(srcdir)/config/arm/cortex-r4f.md \ -- 2.30.2