From d8c79f33416fc5fb680fa74f1bd75abd889ce3aa Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 23 May 2022 07:24:20 +0100
Subject: [PATCH]

---
 openpower/sv/cr_int_predication.mdwn | 20 +++++---------------
 1 file changed, 5 insertions(+), 15 deletions(-)

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 12108c71c..78157e1d1 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -65,17 +65,6 @@ Side-effects:
 * mtcrweird when RA=0 is a means to set or clear arbitrary CR bits
   using immediates embedded within the instruction.
 
-(Twin) Predication interactions:
-
-* INT twin predication with zeroing is a way to copy an integer into
-  CRs without necessarily needing the INT register (RA).  if it is, it is
-  effectively ANDed (or negate-and-ANDed) with the INT Predicate
-* CR twin predication with zeroing is likewise a way to interact with
-  the incoming integer
-
-this gets particularly powerful if data-dependent predication is also
-enabled.  further explanation is below.
-
 # Bit ordering.
 
 Please see [[svp64/appendix]] regarding CR bit ordering and for
@@ -151,10 +140,11 @@ mode is encoded in XO and is 4 bits
 
     mtcrrweird: BF,RA,M,mask,mode
 
-    n0 = mask[0] & (mode[0] == RA[63])
-    n1 = mask[1] & (mode[1] == RA[62])
-    n2 = mask[2] & (mode[2] == RA[61])
-    n3 = mask[3] & (mode[3] == RA[60])
+    a = (RA|0)
+    n0 = mask[0] & (mode[0] == a[63])
+    n1 = mask[1] & (mode[1] == a[62])
+    n2 = mask[2] & (mode[2] == a[61])
+    n3 = mask[3] & (mode[3] == a[60])
     result = n0 || n1 || n2 || n3
     if M:
         result |= CR{BF} & ~mask
-- 
2.30.2