From d8d4e81b6e0624cb7055dbb147a967f5975f294b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 18 Feb 2012 18:56:18 +0100 Subject: [PATCH] bank/csrgen: fix RE generation --- migen/bank/csrgen.py | 1 + 1 file changed, 1 insertion(+) diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py index fed5058d..5f5437f3 100644 --- a/migen/bank/csrgen.py +++ b/migen/bank/csrgen.py @@ -27,6 +27,7 @@ class Bank: self.interface.we & \ (self.interface.adr[:nbits] == Constant(i, BV(nbits))))) elif isinstance(reg, RegisterFields): + sync.append(reg.re.eq(0)) bwra = [Constant(i, BV(nbits))] offset = 0 for field in reg.fields: -- 2.30.2