From d8d58a50a16d7f025bb7d18c1b8727c9131c467d Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 9 Oct 2020 11:32:35 +0100
Subject: [PATCH] change undefined to be a function this therefore "tags"
 locations in the spec with a red flag that need replacing with exact
 (non-undefined) behaviour

---
 openpower/isa/fixedarith.mdwn | 36 +++++++++++++++++------------------
 openpower/isa/stringldst.mdwn |  2 +-
 openpower/isa/system.mdwn     |  4 ++--
 3 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index 9d7bcf78d..0e0ebf68d 100644
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -389,11 +389,11 @@ Pseudo-code:
     if (((dividend = 0x8000_0000) &
          (divisor = 0xffff_ffff)) |
          (divisor = 0x0000_0000)) then
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
         overflow <- 1
     else
         RT[32:63] <- DIVS(dividend, divisor)
-        RT[0:31] <- undef([0]*32)
+        RT[0:31] <- undefined([0]*32)
         overflow <- 0
 
 Special Registers Altered:
@@ -416,10 +416,10 @@ Pseudo-code:
     divisor[0:31] <- (RB)[32:63]
     if divisor != 0 then
         RT[32:63] <-  dividend / divisor
-        RT[0:31] <- undef([0]*32)
+        RT[0:31] <- undefined([0]*32)
         overflow <- 0
     else
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
         overflow <- 1
 
 Special Registers Altered:
@@ -449,12 +449,12 @@ Pseudo-code:
         result32[0:63] <- EXTS64(result[32:63])
         if (result32 = result) then
             RT[32:63] <- result[32:63]
-            RT[0:31] <- undef([0]*32)
+            RT[0:31] <- undefined([0]*32)
             overflow <- 0
         else
             overflow <- 1
     if overflow = 1 then
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
 
 Special Registers Altered:
 
@@ -480,12 +480,12 @@ Pseudo-code:
         result <- dividend / divisor
         if RA[32:63] <u RB[32:63] then
             RT[32:63] <- result[32:63]
-            RT[0:31] <- undef([0]*32)
+            RT[0:31] <- undefined([0]*32)
             overflow <- 0
         else
             overflow <- 1
     if overflow = 1 then
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
 
 Special Registers Altered:
 
@@ -505,11 +505,11 @@ Pseudo-code:
     if (((dividend = 0x8000_0000) &
          (divisor = 0xffff_ffff)) |
          (divisor = 0x0000_0000)) then
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
         overflow <- 1
     else
         RT[0:63] <- EXTS64(MODS(dividend, divisor))
-        RT[0:31] <- undef(RT[0:31])
+        RT[0:31] <- undefined(RT[0:31])
         overflow <- 0
 
 Special Registers Altered:
@@ -527,11 +527,11 @@ Pseudo-code:
     dividend[0:31] <- (RA) [32:63]
     divisor [0:31] <- (RB) [32:63]
     if divisor = 0x0000_0000 then
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
         overflow <- 1
     else
         RT[32:63] <- dividend % divisor
-        RT[0:31] <- undef([0]*32)
+        RT[0:31] <- undefined([0]*32)
         overflow <- 0
 
 Special Registers Altered:
@@ -669,7 +669,7 @@ Pseudo-code:
     if (((dividend = 0x8000_0000_0000_0000) &
          (divisor = 0xffff_ffff_ffff_ffff)) |
          (divisor = 0x0000_0000_0000_0000)) then
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
         overflow <- 1
     else
         RT <- DIVS(dividend, divisor)
@@ -694,7 +694,7 @@ Pseudo-code:
     dividend[0:63] <- (RA)
     divisor[0:63] <- (RB)
     if (divisor = 0x0000_0000_0000_0000) then
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
         overflow <- 1
     else
         RT <- dividend / divisor
@@ -731,7 +731,7 @@ Pseudo-code:
         else
             overflow <- 1
     if overflow = 1 then
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
 
 Special Registers Altered:
 
@@ -761,7 +761,7 @@ Pseudo-code:
         else
             overflow <- 1
     if overflow = 1 then
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
 
 Special Registers Altered:
 
@@ -781,7 +781,7 @@ Pseudo-code:
     if (((dividend = 0x8000_0000_0000_0000) &
          (divisor = 0xffff_ffff_ffff_ffff)) |
          (divisor = 0x0000_0000_0000_0000)) then
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
         overflow <- 1
     else
         RT       <- MODS(dividend, divisor)
@@ -802,7 +802,7 @@ Pseudo-code:
     dividend <- (RA)
     divisor  <- (RB)
     if (divisor = 0x0000_0000_0000_0000) then
-        RT[0:63] <- undef([0]*64)
+        RT[0:63] <- undefined([0]*64)
         overflow <- 1
     else
         RT       <- dividend % divisor
diff --git a/openpower/isa/stringldst.mdwn b/openpower/isa/stringldst.mdwn
index 9a7ac1af0..04723e2e1 100644
--- a/openpower/isa/stringldst.mdwn
+++ b/openpower/isa/stringldst.mdwn
@@ -38,7 +38,7 @@ Pseudo-code:
     n <- XER[57:63]
     r <- RT - 1
     i <- 32
-    RT <- undefined
+    RT <- undefined([0]*64)
     do while n > 0
         if i = 32 then
             r <-  (r + 1) % 32
diff --git a/openpower/isa/system.mdwn b/openpower/isa/system.mdwn
index 2d6d6173f..df853c143 100644
--- a/openpower/isa/system.mdwn
+++ b/openpower/isa/system.mdwn
@@ -28,8 +28,8 @@ SC-Form
 Pseudo-code:
 
     LR <- CIA + 4
-    SRR1[33:36] <- undefined
-    SRR1[42:47] <- undefined
+    SRR1[33:36] <- undefined([0]*4)
+    SRR1[42:47] <- undefined([0]*6)
     SRR1[0:32]  <- MSR[0:32]
     SRR1[37:41] <- MSR[37:41]
     SRR1[48:63] <- MSR[48:63]
-- 
2.30.2