From d8ed1d1a2c507590cf66af8c5a5dd3c5318814ca Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Tue, 25 Jun 2013 00:32:04 -0500 Subject: [PATCH] ruby: moesi cmp directory: separate actions for external hits This patch adds separate actions for requests that missed in the local cache and messages were sent out to get the requested line. These separate actions are required for differentiating between the hit and miss latencies in the statistics collected. --- .../protocol/MOESI_CMP_directory-L1cache.sm | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 5b09e220f..ec6576693 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -629,6 +629,12 @@ machine(L1Cache, "Directory protocol") sequencer.readCallback(address, cache_entry.DataBlk); } + action(hx_load_hit, "hx", desc="Notify sequencer the load completed.") { + assert(is_valid(cache_entry)); + DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); + sequencer.readCallback(address, cache_entry.DataBlk, true); + } + action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); @@ -636,6 +642,13 @@ machine(L1Cache, "Directory protocol") cache_entry.Dirty := true; } + action(xx_store_hit, "\xx", desc="Notify sequencer that store completed.") { + assert(is_valid(cache_entry)); + DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); + sequencer.writeCallback(address, cache_entry.DataBlk, true); + cache_entry.Dirty := true; + } + action(i_allocateTBE, "i", desc="Allocate TBE") { check_allocate(TBEs); TBEs.allocate(address); @@ -1162,7 +1175,7 @@ machine(L1Cache, "Directory protocol") } transition(OM, All_acks, MM_W) { - hh_store_hit; + xx_store_hit; gg_sendUnblockExclusive; s_deallocateTBE; o_scheduleUseTimeout; @@ -1183,7 +1196,7 @@ machine(L1Cache, "Directory protocol") transition(IS, Data, S) { u_writeDataToCache; m_decrementNumberOfMessages; - h_load_hit; + hx_load_hit; g_sendUnblock; s_deallocateTBE; n_popResponseQueue; @@ -1192,7 +1205,7 @@ machine(L1Cache, "Directory protocol") transition(IS, Exclusive_Data, M_W) { u_writeDataToCache; m_decrementNumberOfMessages; - h_load_hit; + hx_load_hit; gg_sendUnblockExclusive; o_scheduleUseTimeout; s_deallocateTBE; -- 2.30.2