From d9056f72a2b7bd1e72c551ac9c86915b9221733e Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 17 May 2021 13:57:28 +0100
Subject: [PATCH] remove MISSING (theyre not), fix a couple of errors in
 pseudocode for lmw and stmw, these are not supported but are there for spec
 "completeness"

---
 openpower/isa/fixedload.mdwn  | 13 +------------
 openpower/isa/fixedstore.mdwn | 11 +----------
 2 files changed, 2 insertions(+), 22 deletions(-)

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 5a64265a..203c1f39 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -435,8 +435,6 @@ Special Registers Altered:
 
     None
 
-<!-- MISSING stq -->
-
 <!-- Section 3.3.5 Fixed-Point Load and Store with Byte Reversal Instructions page 60 -->
 
 # Load Halfword Byte-Reverse Indexed
@@ -456,8 +454,6 @@ Special Registers Altered:
 
     None
 
-<!-- MISSING sthbrx -->
-
 # Load Word Byte-Reverse Indexed
 
 X-Form
@@ -476,8 +472,6 @@ Special Registers Altered:
 
     None
 
-<!-- MISSING stwbrx -->
-
 
 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 
@@ -501,8 +495,6 @@ Special Registers Altered:
 
     None
 
-<!-- MISSING stdbrx -->
-
 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 
 # Load Multiple Word
@@ -515,7 +507,7 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + EXTS(D)
-    r <- RT
+    r <- RT[0:63]
     do while r <=  31
         GPR(r) <- [0]*32 || MEM(EA, 4)
         r <- r + 1
@@ -525,6 +517,3 @@ Special Registers Altered:
 
     None
 
-<!-- MISSING stmw -->
-
-
diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn
index ce64d4b9..d13fa938 100644
--- a/openpower/isa/fixedstore.mdwn
+++ b/openpower/isa/fixedstore.mdwn
@@ -12,15 +12,6 @@
 <!-- Section 3.3.5.1 64-Bit Load and Store with Byte Reversal Instructions page 61 -->
 <!-- Section 3.3.6 Fixed-Point Load and Store Multiple Instructions page 62 -->
 
-<!-- MISSING stbh -->
-<!-- MISSING stbhx -->
-<!-- MISSING stbhu -->
-<!-- MISSING stbhux -->
-<!-- MISSING stbw -->
-<!-- MISSING stbwx -->
-<!-- MISSING stbwu -->
-<!-- MISSING stbwux -->
-
 <!-- Section 3.3.3 Fixed-Point Store Instructions pages 54 - 57 -->
 
 # Store Byte
@@ -380,7 +371,7 @@ Pseudo-code:
 
     b <- (RA|0)
     EA <- b + EXTS(D)
-    r <- RS
+    r <- RS[0:63]
     do while r <= 31
         MEM(EA, 4) <- GPR(r)[32:63]
         r <-  r + 1
-- 
2.30.2