From d905e71c5c7ca84210d4b2609ab2eb01bb11e3f3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 18 Mar 2022 09:16:24 +0000 Subject: [PATCH] remove redundant implementation of migen "timeline" (this is the 2nd copy seen in the wild, the other is in GRAM by Jean-Thomas) --- lambdasoc/periph/hyperram.py | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py index f20f06e..2fdf656 100644 --- a/lambdasoc/periph/hyperram.py +++ b/lambdasoc/periph/hyperram.py @@ -40,30 +40,6 @@ from nmigen_soc.memory import MemoryMap from lambdasoc.periph import Peripheral -# for Migen compat -def timeline(m, trigger, events): - lastevent = max([e[0] for e in events]) - counter = Signal(range(lastevent+1)) - - # insert counter reset if it doesn't naturally overflow - # (test if lastevent+1 is a power of 2) - with m.If(((lastevent & (lastevent + 1)) != 0) & (counter == lastevent)): - m.d.sync += counter.eq(0) - with m.Elif(counter != 0): - m.d.sync += counter.eq(counter + 1) - with m.Elif(trigger): - m.d.sync += counter.eq(1) - - def get_cond(e): - if e[0] == 0: - return trigger & (counter == 0) - else: - return counter == e[0] - for ev in events: - with m.If(get_cond(ev)): - m.d.sync += ev[1] - - # HyperRAM ASIC PHY ----------------------------------------------------------- class HyperRAMASICPhy(Elaboratable): -- 2.30.2