From d914fd349e62bf200a1fda1bc44b38c71dc7e41b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 24 May 2023 12:23:50 +0100 Subject: [PATCH] rename ls006 to ls006.fpintmv --- openpower/sv/rfc/{ls006.mdwn => ls006.fpintmv.mdwn} | 2 +- openpower/sv/rfc/ls012.mdwn | 4 ++-- openpower/sv/rfc/ls012/optable.csv | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) rename openpower/sv/rfc/{ls006.mdwn => ls006.fpintmv.mdwn} (98%) diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.fpintmv.mdwn similarity index 98% rename from openpower/sv/rfc/ls006.mdwn rename to openpower/sv/rfc/ls006.fpintmv.mdwn index d903b9e8e..5e8255cf7 100644 --- a/openpower/sv/rfc/ls006.mdwn +++ b/openpower/sv/rfc/ls006.fpintmv.mdwn @@ -3,7 +3,7 @@ **URLs**: * -* +* * * diff --git a/openpower/sv/rfc/ls012.mdwn b/openpower/sv/rfc/ls012.mdwn index 84b54bd09..1db6df759 100644 --- a/openpower/sv/rfc/ls012.mdwn +++ b/openpower/sv/rfc/ls012.mdwn @@ -82,7 +82,7 @@ Audio/Visual, High-Performance Compute, GPU workloads and DSP. |-|-----------------------------------------------|--------|-------------------| | 6 | SVP64 Management |[[ls008]]
[[ls009]]
[[ls010]] | | | 5 | CR weirds | [[ls015]] | [[sv/cr_int_predication]] | -| 4 | INT<->FP mv | [[ls006]] | | +| 4 | INT<->FP mv | [[ls006.fpintmv]] | | | 19 | GPR LD/ST-PostIncrement-Update (saves hugely in hot-loops) | [[ls011]] | | | ~12 | FPR LD/ST-PostIncrement-Update (ditto) | [[ls011]] | | | 11 | GPR LD/ST-Shifted-PostIncrement-Update (saves in hot-loops) | [[ls011]] | | @@ -298,7 +298,7 @@ omission based on the assumption that VSX would always be present is an equivalent to `xvtstdcsp`. Similar arguments apply to the GPR-INT move operations, proposed in -[[ls006]], with the opportunity taken to add rounding modes present +[[ls006.fpintmv]], with the opportunity taken to add rounding modes present in other ISAs that Power ISA VSX PackedSIMD does not have. Javascript rounding, one of the worst offenders of Computer Science, requires a phenomenal 35 instructions with *six branches* to emulate in Power diff --git a/openpower/sv/rfc/ls012/optable.csv b/openpower/sv/rfc/ls012/optable.csv index 9ead45f8d..97194cf74 100644 --- a/openpower/sv/rfc/ls012/optable.csv +++ b/openpower/sv/rfc/ls012/optable.csv @@ -126,10 +126,10 @@ mcrfm, ls015, high, 9, yes, EXT0xx, no, sv/cr_int_predication, 2r1w, SFFS, T # fclass (Scalar variant of xvtstdcsp) fptstp(s), TBD, high, 10, yes, EXT0xx, no, sv/fclass, 1R1w, SFFS, TODO # INT<->FP mv, TBD -fmvtg(s), ls006, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO -fmvfg(s), ls006, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO -fcvtfg(s), ls006, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO -fcvttg(s), ls006, high, 9, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO +fmvtg(s), ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO +fmvfg(s), ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO +fcvtfg(s), ls006.fpintmv, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO +fcvttg(s), ls006.fpintmv, high, 9, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w, SFFS, TODO # Big-Integer Chained 3-in 2-out (64-bit Carry) dsld, ls003.bignum, high, 5, yes, EXT0xx, no, sv/biginteger, 3R2W1w, SFFS, yes dsrd, ls003.bignum, high, 5, yes, EXT0xx, no, sv/biginteger, 3R2W1w, SFFS, yes -- 2.30.2