From d922170458525484ecbd606916d47ecb7b9127a4 Mon Sep 17 00:00:00 2001 From: Stuart Olsen Date: Mon, 6 Apr 2020 22:22:09 -0700 Subject: [PATCH] back.pysim: Reuse clock simulation commands --- nmigen/back/pysim.py | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py index 398266e..f0fa2da 100644 --- a/nmigen/back/pysim.py +++ b/nmigen/back/pysim.py @@ -1021,11 +1021,14 @@ class Simulator: # Behave correctly if the process is added after the clock signal is manipulated, or if # its reset state is high. initial = (yield domain.clk) + steps = ( + domain.clk.eq(~initial), + Delay(half_period), + domain.clk.eq(initial), + Delay(half_period), + ) while True: - yield domain.clk.eq(~initial) - yield Delay(half_period) - yield domain.clk.eq(initial) - yield Delay(half_period) + yield from iter(steps) self._add_coroutine_process(clk_process, default_cmd=None) self._clocked.add(domain) -- 2.30.2