From d9236ccce86fd4e76552b89390c353d1657eee6f Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 27 Jul 2022 15:06:25 +0100 Subject: [PATCH] --- openpower/sv/int_fp_mv.mdwn | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn index aff94f83b..e5ea9c035 100644 --- a/openpower/sv/int_fp_mv.mdwn +++ b/openpower/sv/int_fp_mv.mdwn @@ -159,8 +159,8 @@ allowing clearing FPRs. `fmvis` fits with DX-Form: -| 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form | -|--------|------|-------|-------|-------|-----|-----| +| 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form | +|--------|------|-------|-------|-------|-----|---------| | Major | FRS | d1 | d0 | XO | d2 | DX-Form | Pseudocode: @@ -169,14 +169,14 @@ Pseudocode: fp32 = bf16 || [0]*16 # convert BF16 to FP32 FRS = DOUBLE(fp32) # convert FP32 to FP64 -## Float Replace Lower-Half Single, Immediate +## Float Immediate Second-Half MV -`frlsi FRS, D` +`fishmv FRS, D` DX-Form: -| 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form | -|--------|------|-------|-------|-------|-----|-----| +| 0-5 | 6-10 | 11-15 | 16-25 | 26-30 | 31 | Form | +|--------|------|-------|-------|-------|-----|---------| | Major | FRS | d1 | d0 | XO | d2 | DX-Form | Strategically similar to how `oris` is used to construct @@ -184,11 +184,11 @@ Strategically similar to how `oris` is used to construct inserted into `FRS` to extend its accuracy to a full FP32 (stored as usual in FP64 Format within the FPR). If a prior `fmvis` instruction had been used to -set the upper 16-bits of an FP32 value, `frlsi` contains the +set the upper 16-bits of an FP32 value, `fishmv` contains the lower 16-bits. The key difference between using `li` and `oris` to construct 32-bit -GPR Immediates and `frlsi` is that the `fmvis` will have converted +GPR Immediates and `fishmv` is that the `fmvis` will have converted the `BF16` immediate to FP64 (Double) format. This is taken into consideration as can be seen in the pseudocode below. @@ -199,7 +199,7 @@ Pseudocode: n = fp32[0:15] || d0 || d1 || d2 # replace mantissa LSBs FRS = DOUBLE(n) # convert back to FP64 -*This instruction performs a Read-Modify-Write. FRS is read, the additional +**This instruction performs a Read-Modify-Write.** *FRS is read, the additional 16 bit immediate inserted, and the result also written to FRS* Example: @@ -211,7 +211,7 @@ Example: # first the upper bits, happens to be +1.0 fmvis f4, 0x3F80 # writes +1.0 to f4 # now write the lower 16 bits of an FP32 -frlsi f4, 0x8000 # writes +1.00390625 to f4 +fishmv f4, 0x8000 # writes +1.00390625 to f4 ``` # Moves -- 2.30.2