From d92ae15d19f598566dda51917d1cf52e34165fce Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 8 Sep 2022 15:14:10 +0100 Subject: [PATCH] --- openpower/sv/rfc/001.mdwn | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/openpower/sv/rfc/001.mdwn b/openpower/sv/rfc/001.mdwn index c6fb3de1f..6d5e61cdd 100644 --- a/openpower/sv/rfc/001.mdwn +++ b/openpower/sv/rfc/001.mdwn @@ -23,6 +23,21 @@ A variant of Simple-V was originally invented in 1994 by Peter Hsu (Architect of the MIPS R8000) but was dropped as MIPS did not have an Out-of-Order Microarchitecture. +Simple-V is designed for Embedded Scenarios right the way through +Audio/Visual DSPs to 3D GPUs and Supercomputing. As it does **not** +add actual Vector Instructions, relying solely and exclusively on the +**Scalar** ISA, it is **Scalar** instructions that need to be added +to the **Scalar** Power ISA before Simple-V may orthogonally Vectorise +them. + +Therefore because the goal of RED Semiconductor Ltd, an OpenPOWER Stakeholder, +is to bring to market mass-volume general-purpose compute processors that +are competitive in the 3D GPU Audio Visual DSP EDGE IoT markets, Simple-V +has to be accompanied by corresponding **Scalar** instructions that bring +the **Scalar** Power ISA up-to-date. These include IEEE754 Transcendentals +AV cryptographic Biginteger and bitmanipulation operations that ARM Intel +AMD and many other ISAs have been adding over the past 12 years. + # Resources -- 2.30.2