From d92bd8ffaa9a9d1f3d51498c8e382f7041e69274 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 12 Jan 2020 22:06:35 +0100 Subject: [PATCH] gen/fhdl/verilog: fix signed init values --- litex/gen/fhdl/verilog.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index e1bd8da4..f515dbfb 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -59,8 +59,8 @@ def _printsig(ns, s): def _printconstant(node): if node.signed: - return (str(node.nbits) + "'sd" + str(2**node.nbits + node.value), - True) + sign = "-" if node.value < 0 else "" + return (sign + str(node.nbits) + "'d" + str(abs(node.value)), True) else: return str(node.nbits) + "'d" + str(node.value), False -- 2.30.2