From d9449b2010573b4be53a9b4ef0567238f4551d9d Mon Sep 17 00:00:00 2001 From: Konstantinos Margaritis Date: Thu, 4 May 2023 15:38:33 +0000 Subject: [PATCH] merge maddrs/msubrs, unit tests changed accordingly --- openpower/isa/butterfly.mdwn | 47 +++++++---------------- openpower/isatables/minor_22.csv | 1 - src/openpower/decoder/isa/caller.py | 2 +- src/openpower/decoder/power_enums.py | 2 - src/openpower/test/alu/maddsubrs_cases.py | 10 ++--- 5 files changed, 18 insertions(+), 44 deletions(-) diff --git a/openpower/isa/butterfly.mdwn b/openpower/isa/butterfly.mdwn index ec106793..726151b8 100644 --- a/openpower/isa/butterfly.mdwn +++ b/openpower/isa/butterfly.mdwn @@ -52,44 +52,23 @@ Pseudo-code: prod_lo <- prod[XLEN:(XLEN*2)-1] if n = 0 then RT <- (RT) + prod_lo + RS <- (RS) - prod_lo else - res <- (RT) + prod_lo + res1 <- (RT) + prod_lo + res2 <- (RS) - prod_lo round <- [0]*XLEN round[XLEN -n] <- 1 - res <- res + round - signbit <- res[0] + res1 <- res1 + round + res2 <- res2 + round + signbit1 <- res1[0] + signbit2 <- res2[0] m <- MASK(n, (XLEN-1)) - res <- ROTL64(res, XLEN-n) & m - smask <- ([signbit]*XLEN) & ¬m - RT <- (res | smask) - -Special Registers Altered: - - None - -# [DRAFT] Integer Butterfly Multiply Subtract From FFT/DCT - -A-Form - -* msubrs RT,RA,SH,RB - -Pseudo-code: - - n <- SH - prod <- MULS(RB, RA) - prod_lo <- prod[XLEN:(XLEN*2)-1] - if n = 0 then - RT <- (RT) - prod_lo - else - res <- (RT) - prod_lo - round <- [0]*XLEN - round[XLEN -n] <- 1 - res <- res + round - signbit <- res[0] - m <- MASK(n, (XLEN-1)) - res <- ROTL64(res, XLEN-n) & m - smask <- ([signbit]*XLEN) & ¬m - RT <- (res | smask) + res1 <- ROTL64(res1, XLEN-n) & m + res2 <- ROTL64(res2, XLEN-n) & m + smask1 <- ([signbit1]*XLEN) & ¬m + smask2 <- ([signbit2]*XLEN) & ¬m + RT <- (res1 | smask1) + RS <- (res2 | smask2) Special Registers Altered: diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv index 1ba448b7..a2a6e8fe 100644 --- a/openpower/isatables/minor_22.csv +++ b/openpower/isatables/minor_22.csv @@ -42,4 +42,3 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou -----01011-,ALU,OP_FISHMV,FRS,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fishmv,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg ------01000,ALU,OP_MADDSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddsubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg ------01001,ALU,OP_MADDRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg -------01010,ALU,OP_MSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,msubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 101a2ad0..48f5ed1e 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1920,7 +1920,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): "fmvtg", "fmvtgs", "fcvtfg", "fcvtfgs", "fmvfg", "fmvfgs", - "maddsubrs", "maddrs", "msubrs" + "maddsubrs", "maddrs" ]: illegal = False ins_name = dotstrp diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index ebd23321..ed635424 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -758,7 +758,6 @@ _insns = [ "maddhd", "maddhdu", "maddld", # INT multiply-and-add "maddsubrs", # Integer DCT Butterfly Add Sub and Round Shift "maddrs", # Integer DCT Butterfly Add and Accumulate and Round Shift - "msubrs", # Integer DCT Butterfly Subtract From and Round Shift "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs "mfmsr", "mfspr", "minmax", # AV bitmanip @@ -922,7 +921,6 @@ class MicrOp(Enum): OP_SHADD = 103 OP_MADDSUBRS = 104 OP_MADDRS = 105 - OP_MSUBRS = 106 class In1Sel(Enum): diff --git a/src/openpower/test/alu/maddsubrs_cases.py b/src/openpower/test/alu/maddsubrs_cases.py index f4433fcb..366d63a7 100644 --- a/src/openpower/test/alu/maddsubrs_cases.py +++ b/src/openpower/test/alu/maddsubrs_cases.py @@ -94,8 +94,7 @@ class MADDSUBRSTestCase(TestAccumulatorBase): def case_0_maddrs(self): isa = SVP64Asm(["maddsubrs 1,10,0,11", - "maddrs 1,10,0,12", - "msubrs 2,10,0,12"]) + "maddrs 1,10,0,12"]) lst = list(isa) initial_regs = [0] * 32 @@ -104,7 +103,7 @@ class MADDSUBRSTestCase(TestAccumulatorBase): initial_regs[11] = 0x00002d41 initial_regs[12] = 0x00000d00 - e = ExpectedState(pc=12) + e = ExpectedState(pc=8) e.intregs[1] = 0x3658c869 e.intregs[2] = 0xffffffffcd583ef9 e.intregs[10] = 0x0000e6b8 @@ -114,8 +113,7 @@ class MADDSUBRSTestCase(TestAccumulatorBase): def case_1_maddrs(self): isa = SVP64Asm(["maddsubrs 1,10,0,11", - "maddrs 1,10,14,12", - "msubrs 2,10,14,12"]) + "maddrs 1,10,14,12"]) lst = list(isa) initial_regs = [0] * 32 @@ -124,7 +122,7 @@ class MADDSUBRSTestCase(TestAccumulatorBase): initial_regs[11] = 0x00002d41 initial_regs[12] = 0x00000d00 - e = ExpectedState(pc=12) + e = ExpectedState(pc=8) e.intregs[1] = 0x0000d963 e.intregs[2] = 0xffffffffffff3561 e.intregs[10] = 0x0000e6b8 -- 2.30.2