From d963bbbdec4fb3b1dbe9b3206c3c153a07c6f8cb Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 26 Sep 2020 19:44:42 +0100 Subject: [PATCH] add alternative PowerDecode2 to branch test_pipe_caller --- src/soc/fu/branch/test/test_pipe_caller.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index c7430445..21c71056 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -151,6 +151,11 @@ class TestRunner(unittest.TestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name) pdecode = pdecode2.dec + # copy of the decoder for simulator + simdec = create_pdecode() + simdec2 = PowerDecode2(simdec) + m.submodules.simdec2 = simdec2 # pain in the neck + pspec = BranchPipeSpec(id_wid=2) m.submodules.branch = branch = BranchBasePipe(pspec) @@ -167,7 +172,7 @@ class TestRunner(unittest.TestCase): print(test.name) program = test.program with self.subTest(test.name): - simulator = ISA(pdecode2, test.regs, test.sprs, test.cr, + simulator = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem, test.msr, bigendian=bigendian) initial_cia = 0x2000 @@ -214,7 +219,8 @@ class TestRunner(unittest.TestCase): index = (pc - initial_cia)//4 yield from self.assert_outputs(branch, pdecode2, - simulator, prev_nia, code) + simulator, prev_nia, + code) sim.add_sync_process(process) with sim.write_vcd("branch_simulator.vcd"): -- 2.30.2