From d969a9060eb337007e9246301fff906db5a8283e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 15 Jun 2019 22:41:29 -0700 Subject: [PATCH] Add +/xilinx/abc_ff --- techlibs/xilinx/abc_ff.v | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 techlibs/xilinx/abc_ff.v diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v new file mode 100644 index 000000000..abf4ac093 --- /dev/null +++ b/techlibs/xilinx/abc_ff.v @@ -0,0 +1,33 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * 2019 Eddie Hung + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +// ============================================================================ + +module \$__ABC_FF_ (input C, D, output Q); +endmodule + +(* abc_box_id = 6, lib_whitebox, abc_flop *) +module \$__ABC_FDRE ((* abc_flop_q *) output Q, input C, CE, (* abc_flop_d *) input D, (* abc_flop_q_past, abc_discard *) input Q_past, input R); + parameter [0:0] INIT = 1'b0; + //parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : Q_past); +endmodule -- 2.30.2