From d97a640b53901765c9d8a3d26080321e43d91ec7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 16 Sep 2012 11:49:16 +0200 Subject: [PATCH] add ramp / square / sinus signal generation in examples --- examples/de0_nano/client/test_MigIo.py | 50 ++++++++++++++-------- examples/de0_nano/constraints.py | 3 -- examples/de0_nano/de0_nano.qpf | 29 +------------ examples/de0_nano/de0_nano.sdc | 1 - examples/de0_nano/top.py | 51 +++++++++++++++++++---- examples/de1/client/test_MigLa.py | 57 +++++++++++++++++--------- examples/de1/de1.qpf | 29 +------------ examples/de1/de1.sdc | 1 - examples/de1/top.py | 31 ++++++-------- 9 files changed, 128 insertions(+), 124 deletions(-) diff --git a/examples/de0_nano/client/test_MigIo.py b/examples/de0_nano/client/test_MigIo.py index 5eee23cf..c37229f7 100644 --- a/examples/de0_nano/client/test_MigIo.py +++ b/examples/de0_nano/client/test_MigIo.py @@ -22,34 +22,48 @@ dat_width = 16 # Record Size record_size = 1024 +csr = Uart2Spi(1,115200) + # Csr Addr MIGIO0_ADDR = 0x0000 -TRIGGER_ADDR = 0x0200 -RECORDER_ADDR = 0x0400 # MigScope Configuration # migIo -migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO") +migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO", csr) -# Trigger -term0 = trigger.Term(trig_width) -trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0]) +def led_anim0(): + for i in range(10): + migIo0.write(0xA5) + time.sleep(0.1) + migIo0.write(0x5A) + time.sleep(0.1) -# Recorder -recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size) +def led_anim1(): + #Led << + for j in range(4): + ledData = 1 + for i in range(8): + migIo0.write(ledData) + time.sleep(i*i*0.0020) + ledData = (ledData<<1) + #Led >> + ledData = 128 + for i in range(8): + migIo0.write(ledData) + time.sleep(i*i*0.0020) + ledData = (ledData>>1) #============================================================================== # T E S T M I G I O #============================================================================== -csr = Uart2Spi(1,115200) +print("- Small Led Animation...") +led_anim0() +time.sleep(1) +led_anim1() +time.sleep(1) + +print("- Read Switch: ",end=' ') +print(migIo0.read()) + -print("1) Write Led Reg") -for i in range(10): - csr.write(MIGIO0_ADDR + 0,0xA5) - time.sleep(0.1) - csr.write(MIGIO0_ADDR + 0,0x5A) - time.sleep(0.1) - -print("2) Read Switch Reg") -print(csr.read(MIGIO0_ADDR + 1)) diff --git a/examples/de0_nano/constraints.py b/examples/de0_nano/constraints.py index 36f7d363..6852f70f 100644 --- a/examples/de0_nano/constraints.py +++ b/examples/de0_nano/constraints.py @@ -49,9 +49,6 @@ class Constraints: set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE EP4CE22F17C6 set_global_assignment -name TOP_LEVEL_ENTITY "de0_nano" -set_global_assignment -name DEVICE_FILTER_PACKAGE FPGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" diff --git a/examples/de0_nano/de0_nano.qpf b/examples/de0_nano/de0_nano.qpf index 82d96c17..39719d05 100644 --- a/examples/de0_nano/de0_nano.qpf +++ b/examples/de0_nano/de0_nano.qpf @@ -1,30 +1,3 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2009 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 9.0 Build 132 02/25/2009 SJ Full Version -# Date created = 11:09:38 March 18, 2009 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "9.0" -DATE = "11:09:38 March 18, 2009" - # Revisions -PROJECT_REVISION = "soc" +PROJECT_REVISION = "de0_nano" diff --git a/examples/de0_nano/de0_nano.sdc b/examples/de0_nano/de0_nano.sdc index 4687410a..d272f85c 100644 --- a/examples/de0_nano/de0_nano.sdc +++ b/examples/de0_nano/de0_nano.sdc @@ -1,4 +1,3 @@ -# Synopsys, Inc. constraint file # # Clocks # diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py index 1b347ac6..8e007f6b 100644 --- a/examples/de0_nano/top.py +++ b/examples/de0_nano/top.py @@ -48,6 +48,8 @@ import spi2Csr from timings import * from constraints import Constraints +from math import sin + #============================================================================== # P A R A M E T E R S #============================================================================== @@ -62,7 +64,7 @@ trig_width = 16 dat_width = 16 # Record Size -record_size = 1024 +record_size = 4096 # Csr Addr MIGIO_ADDR = 0x0000 @@ -97,16 +99,51 @@ def get(): comb = [] sync = [] + # # Signal Generator - sig_gen = Signal(BV(trig_width)) + # + + # Counter + cnt_gen = Signal(BV(8)) + sync += [ + cnt_gen.eq(cnt_gen+1) + ] + + # Square + square_gen = Signal(BV(8)) sync += [ - sig_gen.eq(sig_gen+1) + If(cnt_gen[7], + square_gen.eq(255) + ).Else( + square_gen.eq(0) + ) + ] + + sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)] + print(sinus) + sinus_re = Signal() + sinus_gen = Signal(BV(8)) + comb +=[sinus_re.eq(1)] + sinus_port = MemoryPort(adr=cnt_gen, re=sinus_re, dat_r=sinus_gen) + sinus_mem = Memory(8, 256, sinus_port, init = sinus) + + # Signal Selection + sig_gen = Signal(BV(8)) + comb += [ + If(migIo0.o == 0, + sig_gen.eq(cnt_gen) + ).Elif(migIo0.o == 1, + sig_gen.eq(square_gen) + ).Elif(migIo0.o == 2, + sig_gen.eq(sinus_gen) + ).Else( + sig_gen.eq(0) + ) ] # Led led0 = Signal(BV(8)) - comb += [led0.eq(migIo0.o)] - + comb += [led0.eq(migIo0.o[:8])] # Dat / Trig Bus @@ -130,11 +167,11 @@ def get(): in_rst.eq(~in_rst_n) ] frag = autofragment.from_local() - frag += Fragment(sync=sync,comb=comb) + frag += Fragment(sync=sync,comb=comb,memories=[sinus_mem]) cst = Constraints(in_clk, in_rst_n, spi2csr0, led0) src_verilog, vns = verilog.convert(frag, cst.get_ios(), - name="de0_nano", + name="de1", clk_signal = in_clk, rst_signal = in_rst, return_ns=True) diff --git a/examples/de1/client/test_MigLa.py b/examples/de1/client/test_MigLa.py index e5dbb893..d431ba14 100644 --- a/examples/de1/client/test_MigLa.py +++ b/examples/de1/client/test_MigLa.py @@ -45,28 +45,47 @@ recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size, csr) #============================================================================== # T E S T M I G L A #============================================================================== -term0.write(0x0000) - -sum_tt = gen_truth_table("term0") -trigger0.sum.write(sum_tt) +dat_vcd = [] +recorder0.size(1024) -csr.write(0x0000,0) +def capture(): + global trigger0 + global recorder0 + global dat_vcd + sum_tt = gen_truth_table("term0") + trigger0.sum.write(sum_tt) + recorder0.reset() + recorder0.offset(0) + recorder0.arm() + print("-Recorder [Armed]") + print("-Waiting Trigger...", end = ' ') + while(not recorder0.is_done()): + time.sleep(0.1) + print("[Done]") + + print("-Receiving Data...", end = ' ') + sys.stdout.flush() + dat_vcd += recorder0.read(1024) + print("[Done]") + +print("Capturing Ramp..") +print("----------------------") +term0.write(0x0000) +csr.write(0x0000, 0) +capture() -recorder0.reset() -recorder0.size(1024) -recorder0.offset(0) -recorder0.arm() -print("-Recorder [Armed]") -print("-Waiting Trigger...", end = ' ') -while(not recorder0.is_done()): - time.sleep(0.1) -print("[Done]") +print("Capturing Square..") +print("----------------------") +term0.write(0x0000) +csr.write(0x0000, 1) +capture() -print("-Receiving Data...", end = ' ') -sys.stdout.flush() -dat_vcd = recorder0.read(1024) -print("[Done]") +print("Capturing Sinus..") +print("----------------------") +term0.write(0x0080) +csr.write(0x0000, 2) +capture() myvcd = Vcd() -myvcd.add(Var("wire", 32, "trig_dat", dat_vcd)) +myvcd.add(Var("wire", 16, "trig_dat", dat_vcd)) myvcd.write("test_MigLa.vcd") \ No newline at end of file diff --git a/examples/de1/de1.qpf b/examples/de1/de1.qpf index 82d96c17..716d98fa 100644 --- a/examples/de1/de1.qpf +++ b/examples/de1/de1.qpf @@ -1,30 +1,3 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2009 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 9.0 Build 132 02/25/2009 SJ Full Version -# Date created = 11:09:38 March 18, 2009 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "9.0" -DATE = "11:09:38 March 18, 2009" - # Revisions -PROJECT_REVISION = "soc" +PROJECT_REVISION = "de1" diff --git a/examples/de1/de1.sdc b/examples/de1/de1.sdc index 4687410a..d272f85c 100644 --- a/examples/de1/de1.sdc +++ b/examples/de1/de1.sdc @@ -1,4 +1,3 @@ -# Synopsys, Inc. constraint file # # Clocks # diff --git a/examples/de1/top.py b/examples/de1/top.py index 41480cf0..511db3c0 100644 --- a/examples/de1/top.py +++ b/examples/de1/top.py @@ -48,6 +48,8 @@ import spi2Csr from timings import * from constraints import Constraints +from math import sin + #============================================================================== # P A R A M E T E R S #============================================================================== @@ -118,6 +120,13 @@ def get(): ) ] + sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)] + print(sinus) + sinus_re = Signal() + sinus_gen = Signal(BV(8)) + comb +=[sinus_re.eq(1)] + sinus_port = MemoryPort(adr=cnt_gen, re=sinus_re, dat_r=sinus_gen) + sinus_mem = Memory(8, 256, sinus_port, init = sinus) # Signal Selection sig_gen = Signal(BV(8)) @@ -126,29 +135,13 @@ def get(): sig_gen.eq(cnt_gen) ).Elif(migIo0.o == 1, sig_gen.eq(square_gen) + ).Elif(migIo0.o == 2, + sig_gen.eq(sinus_gen) ).Else( sig_gen.eq(0) ) ] - ramp_gen = Signal(BV(8)) - sync += [ - ramp_gen.eq(ramp_gen+1) - ] - - square_gen = Signal(BV(8)) - sync += [ - - ramp_gen.eq(ramp_gen+1) - ] - - - - - - - #comb += [sig_gen.eq(migIo0.o)] - # Led led0 = Signal(BV(8)) comb += [led0.eq(migIo0.o[:8])] @@ -178,7 +171,7 @@ def get(): in_rst.eq(~in_rst_n) ] frag = autofragment.from_local() - frag += Fragment(sync=sync,comb=comb) + frag += Fragment(sync=sync,comb=comb,memories=[sinus_mem]) cst = Constraints(in_clk, in_rst_n, spi2csr0, led0, sw0) src_verilog, vns = verilog.convert(frag, cst.get_ios(), -- 2.30.2