From d9962d509e33f9a8f242a45f8260a480e51a04e0 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 18 Jun 2020 15:47:12 -0700 Subject: [PATCH] finish code to calculate the 64-bit output of the div pipeline --- src/soc/fu/div/output_stage.py | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/src/soc/fu/div/output_stage.py b/src/soc/fu/div/output_stage.py index aed1bdb1..88a9ec1e 100644 --- a/src/soc/fu/div/output_stage.py +++ b/src/soc/fu/div/output_stage.py @@ -81,18 +81,36 @@ class DivOutputStage(PipeModBase): ########################## # main switch for DIV + o = self.o.o.data + with m.Switch(op.insn_type): - # TODO(programmerjake): finish switch - with m.Case(InternalOp.OP_DIV, InternalOp.OP_DIVE): + with m.Case(InternalOp.OP_DIVE): + with m.If(op.is_32bit): + with m.If(op.is_signed): + # matches POWER9's divweo behavior + comb += o.eq(quotient_64[0:32].as_unsigned()) + with m.Else(): + comb += o.eq(quotient_64[0:32].as_unsigned()) + with m.Else(): + comb += o.eq(quotient_64) + with m.Case(InternalOp.OP_DIV): with m.If(op.is_32bit): - comb += dividend_in.eq(self.abs_dividend[0:32]) + with m.If(op.is_signed): + # matches POWER9's divwo behavior + comb += o.eq(quotient_64[0:32].as_unsigned()) + with m.Else(): + comb += o.eq(quotient_64[0:32].as_unsigned()) with m.Else(): - comb += dividend_in.eq(self.abs_dividend[0:64]) + comb += o.eq(quotient_64) with m.Case(InternalOp.OP_MOD): with m.If(op.is_32bit): - comb += dividend_in.eq(self.abs_dividend[0:32] << 32) + with m.If(op.is_signed): + # matches POWER9's modsw behavior + comb += o.eq(remainder_64[0:32].as_signed()) + with m.Else(): + comb += o.eq(remainder_64[0:32].as_unsigned()) with m.Else(): - comb += dividend_in.eq(self.abs_dividend[0:64] << 64) + comb += o.eq(remainder_64) ###### sticky overflow and context, both pass-through ##### -- 2.30.2