From d99a274dfdc18b11aac25b00ca32b7910061776d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 3 May 2021 13:00:10 +0100 Subject: [PATCH] must only try to connect jtag when variant requests it --- sim.py | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/sim.py b/sim.py index 306adf4..550339e 100755 --- a/sim.py +++ b/sim.py @@ -165,21 +165,22 @@ class LibreSoCSim(SoCSDRAM): self.add_constant("MEMTEST_DATA_DEBUG", 1) - # add JTAG platform pins - platform.add_extension([ - ("jtag", 0, - Subsignal("tck", Pins(1)), - Subsignal("tms", Pins(1)), - Subsignal("tdi", Pins(1)), - Subsignal("tdo", Pins(1)), - ) - ]) + if "jtag" in variant: + # add JTAG platform pins + platform.add_extension([ + ("jtag", 0, + Subsignal("tck", Pins(1)), + Subsignal("tms", Pins(1)), + Subsignal("tdi", Pins(1)), + Subsignal("tdo", Pins(1)), + ) + ]) - jtagpads = platform.request("jtag") - self.comb += self.cpu.jtag_tck.eq(jtagpads.tck) - self.comb += self.cpu.jtag_tms.eq(jtagpads.tms) - self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi) - self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo) + jtagpads = platform.request("jtag") + self.comb += self.cpu.jtag_tck.eq(jtagpads.tck) + self.comb += self.cpu.jtag_tms.eq(jtagpads.tms) + self.comb += self.cpu.jtag_tdi.eq(jtagpads.tdi) + self.comb += jtagpads.tdo.eq(self.cpu.jtag_tdo) # Debug --------------------------------------------------------------- -- 2.30.2