From d99dacc9484b29b9223526264bc055905c31b08c Mon Sep 17 00:00:00 2001 From: Wilco Dijkstra Date: Mon, 27 Jul 2015 15:02:55 +0000 Subject: [PATCH] [PATCH][AArch64] Improve spill code - swap order in shl pattern gcc/ * config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_3): Place integer variant first. From-SVN: r226247 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/aarch64.md | 14 +++++++------- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0a9ae7fef88..00b9b99fa9d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2015-07-27 Wilco Dijkstra + + * config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_3): + Place integer variant first. + 2015-07-27 Matthew Wahab * config/arm/arm-arches.def: Add "armv6kz". Replace 6ZK with 6KZ diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index f2645341410..65e4c66264c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3523,17 +3523,17 @@ ;; Logical left shift using SISD or Integer instruction (define_insn "*aarch64_ashl_sisd_or_int_3" - [(set (match_operand:GPI 0 "register_operand" "=w,w,r") + [(set (match_operand:GPI 0 "register_operand" "=r,w,w") (ashift:GPI - (match_operand:GPI 1 "register_operand" "w,w,r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "Us,w,rUs")))] + (match_operand:GPI 1 "register_operand" "r,w,w") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "rUs,Us,w")))] "" "@ + lsl\t%0, %1, %2 shl\t%0, %1, %2 - ushl\t%0, %1, %2 - lsl\t%0, %1, %2" - [(set_attr "simd" "yes,yes,no") - (set_attr "type" "neon_shift_imm, neon_shift_reg,shift_reg")] + ushl\t%0, %1, %2" + [(set_attr "simd" "no,yes,yes") + (set_attr "type" "shift_reg,neon_shift_imm, neon_shift_reg")] ) ;; Logical right shift using SISD or Integer instruction -- 2.30.2