From d9a6bc9010ef9efda9a8c2849d3b3c88f39d7fc9 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 13 Mar 2022 01:13:04 +0000 Subject: [PATCH] --- openpower/sv/bitmanip.mdwn | 3 --- 1 file changed, 3 deletions(-) diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn index 56e624db3..91e01e08a 100644 --- a/openpower/sv/bitmanip.mdwn +++ b/openpower/sv/bitmanip.mdwn @@ -156,7 +156,6 @@ Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/v ## ternlogi -TODO: if/when we get more encoding space, add Rc=1 option back to ternlogi, for consistency with OpenPower base logical instructions (and./xor./or./etc.). | 0.5|6.10|11.15|16.20| 21..25| 26..30 |31| | -- | -- | --- | --- | ----- | -------- |--| @@ -169,8 +168,6 @@ TODO: if/when we get more encoding space, add Rc=1 option back to ternlogi, for for i in range(64): RT[i] = lut3(imm, RB[i], RA[i], RT[i]) -bits 21..22 may be used to specify a mode, such as treating the whole integer zero/nonzero and putting 1/0 in the result, rather than bitwise test. - ## ternlog a 5 operand variant which becomes more along the lines of an FPGA, -- 2.30.2