From d9abaf326f14a84687aebd021f02ae8aa0225cc1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 12 Jul 2018 11:55:50 +0100 Subject: [PATCH] add slides --- shakti/m_class/libre_riscv_chennai_2018.tex | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex index cbc511e8d..500b38e82 100644 --- a/shakti/m_class/libre_riscv_chennai_2018.tex +++ b/shakti/m_class/libre_riscv_chennai_2018.tex @@ -308,11 +308,10 @@ \begin{itemize} \item GPUs are usually done with incompatible ISAs and effectively doing OpenGL over IPC / RPC (Remote Procedure Calls) - \item Much simpler: GPGPU approach. Custom-extend the - main core ISA to handle 3D, and accelerate - Gallium3D-LLVM. - \item Now add Video Extensions. and SIMD. and, and, and...\\ - {\bf we are well beyond the 2 32-bit custom opcodes} + \item Much simpler: GPGPU "one ISA" approach. Custom-extend the + core ISA to handle 3D, use Gallium3D-LLVM. + \item Now add Video Extensions. and SIMD etc and + {\bf we are well beyond the only 2 available 32-bit custom opcodes} \item Due to the Libre nature of this project, the custom opcode space will be "dominated" by high-profile public hard-forks of gcc, binutils, llvm etc. -- 2.30.2