From d9ad6b728bbc46efd4846d0670e8ae126381bc7a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 30 Dec 2022 13:20:56 +0000 Subject: [PATCH] add misaligned mem test --- src/openpower/decoder/isa/test_mem.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/openpower/decoder/isa/test_mem.py b/src/openpower/decoder/isa/test_mem.py index 4436d07f..bd847c26 100644 --- a/src/openpower/decoder/isa/test_mem.py +++ b/src/openpower/decoder/isa/test_mem.py @@ -9,13 +9,21 @@ from openpower.util import log class TestMem(unittest.TestCase): - def test_mem_align_ld(self): + def test_mem_align_st(self): m = Mem(row_bytes=8, initial_mem={}) m.st(4, 0x12345678, width=4, swap=False) d = m.dump() log ("dict", d) self.assertEqual(d, [(0, 0x1234567800000000)]) + def test_mem_misalign_st(self): + m = Mem(row_bytes=8, initial_mem={}) + m.st(4, 0x912345678, width=8, swap=False) + d = m.dump() + log ("dict", d) + self.assertEqual(d, [(0, 0x1234567800000000), + 8, 0x0000000000000009]) + if __name__ == '__main__': unittest.main() -- 2.30.2