From d9b4ccab6a4a6d711dd75be687bf2c1241b38eb3 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 12 Aug 2020 16:50:03 +0100
Subject: [PATCH] create a RegFileMem class that uses Memory

---
 src/soc/regfile/regfile.py  | 27 +++++++++++++++++++++++++++
 src/soc/regfile/regfiles.py |  9 ++++-----
 2 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index a389132d..be1c7693 100644
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -24,6 +24,7 @@ from nmigen.cli import verilog, rtlil
 from nmigen import Cat, Const, Array, Signal, Elaboratable, Module
 from nmutil.iocontrol import RecordObject
 from nmutil.util import treereduce
+from nmigen import Memory
 
 from math import log
 import operator
@@ -93,6 +94,7 @@ def ortreereduce(tree, attr="data_o"):
 
 
 class RegFileArray(Elaboratable):
+    unary = True
     """ an array-based register file (register having write-through capability)
         that has no "address" decoder, instead it has individual write-en
         and read-en signals (per port).
@@ -166,7 +168,32 @@ class RegFileArray(Elaboratable):
         return list(self)
 
 
+class RegFileMem(Elaboratable):
+    unary = False
+    def __init__(self, width, depth):
+        self.memory = Memory(width=width, depth=depth)
+        self._rdports = {}
+        self._wrports = {}
+
+    def read_port(self, name=None):
+        port = self._rdports[name] = self.memory.read_port()
+        return port
+
+    def write_port(self, name=None):
+        port = self._wrports[name] = self.memory.write_port()
+        return port
+
+    def elaborate(self, platform):
+        m = Module()
+        for name, rp in self._rdports.items():
+            setattr(m.submodules, "rp_"+name, rp)
+        for name, wp in self._wrports.items():
+            setattr(m.submodules, "wp_"+name, wp)
+        return m
+
+
 class RegFile(Elaboratable):
+    unary = False
     def __init__(self, width, depth):
         self.width = width
         self.depth = depth
diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 0f29bb8f..318878fa 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -23,10 +23,9 @@ Links:
 
 # TODO
 
-from soc.regfile.regfile import RegFile, RegFileArray
+from soc.regfile.regfile import RegFile, RegFileArray, RegFileMem
 from soc.regfile.virtual_port import VirtualRegPort
 from soc.decoder.power_enums import SPR
-from nmigen import Memory, Elaboratable
 
 
 # "State" Regfile
@@ -144,7 +143,7 @@ class XERRegs(VirtualRegPort):
 
 
 # SPR Regfile
-class SPRRegs(Memory, Elaboratable):
+class SPRRegs(RegFileMem):
     """SPRRegs
 
     * QTY len(SPRs) 64-bit registers
@@ -155,8 +154,8 @@ class SPRRegs(Memory, Elaboratable):
     def __init__(self):
         n_sprs = len(SPR)
         super().__init__(width=64, depth=n_sprs)
-        self.w_ports = {'spr1': self.write_port()}
-        self.r_ports = {'spr1': self.read_port()}
+        self.w_ports = {'spr1': self.write_port("spr1")}
+        self.r_ports = {'spr1': self.read_port("spr1")}
 
         # make read/write ports look like RegFileArray
         self.w_ports['spr1'].wen = self.w_ports['spr1'].en
-- 
2.30.2