From d9bebf867af78965bb26e6e43b688a33d65a816c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 28 Mar 2019 14:02:35 +0000 Subject: [PATCH] use PassThroughStage instead of making one --- src/add/nmigen_add_experiment.py | 27 +++++++-------------------- src/add/singlepipe.py | 2 +- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index 18423ce9..54b69f83 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -9,7 +9,8 @@ from math import log from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase from fpbase import MultiShiftRMerge, Trigger -from singlepipe import (ControlBase, StageChain, UnbufferedPipeline) +from singlepipe import (ControlBase, StageChain, UnbufferedPipeline, + PassThroughStage) from multipipe import CombMuxOutPipe from multipipe import PriorityCombMuxInPipe @@ -1872,18 +1873,11 @@ class FPADDBasePipe(ControlBase): return m -class FPAddInPassThruStage: - def __init__(self, width, id_wid): - self.width, self.id_wid = width, id_wid - def ispec(self): return FPADDBaseData(self.width, self.id_wid) - def ospec(self): return self.ispec() - def process(self, i): return i - - class FPADDInMuxPipe(PriorityCombMuxInPipe): - def __init__(self, width, id_width, num_rows): + def __init__(self, width, id_wid, num_rows): self.num_rows = num_rows - stage = FPAddInPassThruStage(width, id_width) + def iospec(): return FPADDBaseData(width, id_wid) + stage = PassThroughStage(iospec) PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows) def ports(self): @@ -1896,18 +1890,11 @@ class FPADDInMuxPipe(PriorityCombMuxInPipe): return res -class FPAddOutPassThruStage: - def __init__(self, width, id_wid): - self.width, self.id_wid = width, id_wid - def ispec(self): return FPPackData(self.width, self.id_wid) - def ospec(self): return self.ispec() - def process(self, i): return i - - class FPADDMuxOutPipe(CombMuxOutPipe): def __init__(self, width, id_wid, num_rows): self.num_rows = num_rows - stage = FPAddOutPassThruStage(width, id_wid) + def iospec(): return FPPackData(width, id_wid) + stage = PassThroughStage(iospec) CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows) def ports(self): diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py index 775081f3..28a3810c 100644 --- a/src/add/singlepipe.py +++ b/src/add/singlepipe.py @@ -641,7 +641,7 @@ class PassThroughStage(StageCls): """ a pass-through stage which has its input data spec equal to its output, and "passes through" its data from input to output. """ - def __init__(self, iospec): + def __init__(self, iospecfn): self.iospecfn = iospecfn def ispec(self): return self.iospecfn() def ospec(self): return self.iospecfn() -- 2.30.2