From d9d73d80c1b738b3b30eb40d192f61cbdb0e201f Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Thu, 2 Apr 2015 14:23:30 -0700
Subject: [PATCH] Simplify RV32 comparisons

No need to eliminate the upper 32 bits of the 64-bit x-register, as all
RV32 instructions should sign-extend their results to 64 bits.
---
 riscv/decode.h      | 1 -
 riscv/insns/beq.h   | 2 +-
 riscv/insns/bge.h   | 2 +-
 riscv/insns/bgeu.h  | 2 +-
 riscv/insns/blt.h   | 2 +-
 riscv/insns/bltu.h  | 2 +-
 riscv/insns/bne.h   | 2 +-
 riscv/insns/slt.h   | 2 +-
 riscv/insns/slti.h  | 2 +-
 riscv/insns/sltiu.h | 2 +-
 riscv/insns/sltu.h  | 2 +-
 11 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/riscv/decode.h b/riscv/decode.h
index 5d304a1..55f03ff 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -180,7 +180,6 @@ private:
 #endif
 #define require_accelerator if (unlikely((STATE.mstatus & MSTATUS_XS) == 0)) throw trap_illegal_instruction()
 
-#define cmp_trunc(reg) (reg_t(reg) << (64-xlen))
 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
                              softfloat_exceptionFlags = 0; })
 
diff --git a/riscv/insns/beq.h b/riscv/insns/beq.h
index 7b26488..fd7e061 100644
--- a/riscv/insns/beq.h
+++ b/riscv/insns/beq.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) == cmp_trunc(RS2))
+if(RS1 == RS2)
   set_pc(BRANCH_TARGET);
diff --git a/riscv/insns/bge.h b/riscv/insns/bge.h
index dca544b..da0c68e 100644
--- a/riscv/insns/bge.h
+++ b/riscv/insns/bge.h
@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RS1)) >= sreg_t(cmp_trunc(RS2)))
+if(sreg_t(RS1) >= sreg_t(RS2))
   set_pc(BRANCH_TARGET);
diff --git a/riscv/insns/bgeu.h b/riscv/insns/bgeu.h
index 6325466..d764a34 100644
--- a/riscv/insns/bgeu.h
+++ b/riscv/insns/bgeu.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) >= cmp_trunc(RS2))
+if(RS1 >= RS2)
   set_pc(BRANCH_TARGET);
diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h
index d84fd7a..c54fb76 100644
--- a/riscv/insns/blt.h
+++ b/riscv/insns/blt.h
@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)))
+if(sreg_t(RS1) < sreg_t(RS2))
   set_pc(BRANCH_TARGET);
diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h
index 250fd4f..ff75e8a 100644
--- a/riscv/insns/bltu.h
+++ b/riscv/insns/bltu.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) < cmp_trunc(RS2))
+if(RS1 < RS2)
   set_pc(BRANCH_TARGET);
diff --git a/riscv/insns/bne.h b/riscv/insns/bne.h
index f775721..1e6cb7c 100644
--- a/riscv/insns/bne.h
+++ b/riscv/insns/bne.h
@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) != cmp_trunc(RS2))
+if(RS1 != RS2)
   set_pc(BRANCH_TARGET);
diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index dd6e58e..25ccd45 100644
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-WRITE_RD(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)));
+WRITE_RD(sreg_t(RS1) < sreg_t(RS2));
diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 18d32da..3671d24 100644
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-WRITE_RD(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(insn.i_imm())));
+WRITE_RD(sreg_t(RS1) < sreg_t(insn.i_imm()));
diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index ff4eae1..c4478fd 100644
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-WRITE_RD(cmp_trunc(RS1) < cmp_trunc(insn.i_imm()));
+WRITE_RD(RS1 < insn.i_imm());
diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h
index 3a353fd..84d97a2 100644
--- a/riscv/insns/sltu.h
+++ b/riscv/insns/sltu.h
@@ -1 +1 @@
-WRITE_RD(cmp_trunc(RS1) < cmp_trunc(RS2));
+WRITE_RD(RS1 < RS2);
-- 
2.30.2