From d9dc40fe48aff2c862c884eba200620c943fada1 Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Mon, 25 May 2020 15:14:34 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise
 that RA (src1) can be zero

---
 b9/a5c1b482a872319d8a3c9c1834d4ef28cc610e | 67 +++++++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 b9/a5c1b482a872319d8a3c9c1834d4ef28cc610e

diff --git a/b9/a5c1b482a872319d8a3c9c1834d4ef28cc610e b/b9/a5c1b482a872319d8a3c9c1834d4ef28cc610e
new file mode 100644
index 0000000..3892875
--- /dev/null
+++ b/b9/a5c1b482a872319d8a3c9c1834d4ef28cc610e
@@ -0,0 +1,67 @@
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+From: bugzilla-daemon@libre-soc.org
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+Date: Mon, 25 May 2020 15:14:34 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: cestrauss@gmail.com
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+Message-ID: <bug-336-13-O8lbIuAecv@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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-- 
2.30.2