From d9dd01abb7de7a70867eeb289c3019fa3c0337e8 Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Fri, 10 Jul 2020 19:20:20 +0200 Subject: [PATCH] Fix memtest tests (missing parenthesis) --- gram/test/test_soc.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py index bf5b887..0841ea2 100644 --- a/gram/test/test_soc.py +++ b/gram/test/test_soc.py @@ -229,11 +229,11 @@ class SocTestCase(FHDLTestCase): # Write for i in range(n): - yield from wb_write(soc.bus, 0x10000000 >> 2 + i, memtest_values[i], 0xF, 256) + yield from wb_write(soc.bus, (0x10000000 >> 2) + i, memtest_values[i], 0xF, 256) # Read for i in range(n): - self.assertEqual(memtest_values[i], (yield from wb_read(soc.bus, 0x10000000 >> 2 + i, 0xF, 256))) + self.assertEqual(memtest_values[i], (yield from wb_read(soc.bus, (0x10000000 >> 2) + i, 0xF, 256))) runSimulation(m, process, "test_soc_random_memtest.vcd") @@ -251,10 +251,10 @@ class SocTestCase(FHDLTestCase): # Write for i in range(n): - yield from wb_write(soc.bus, 0x10000000 >> 2 + i, 0xFACE0000 | i, 0xF, 256) + yield from wb_write(soc.bus, (0x10000000 >> 2) + i, 0xFACE0000 | i, 0xF, 256) # Read for i in range(n): - self.assertEqual(0xFACE0000 | i, (yield from wb_read(soc.bus, 0x10000000 >> 2 + i, 0xF, 256))) + self.assertEqual(0xFACE0000 | i, (yield from wb_read(soc.bus, (0x10000000 >> 2) + i, 0xF, 256))) runSimulation(m, process, "test_soc_continuous_memtest.vcd") -- 2.30.2